參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 39/137頁
文件大小： 2145K
代理商： 7641
38
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 31 DMACx (x = 0, 1) block diagram
DMAC
The 7641 group is equipped with 2 channels of DMAC (direct
memory access controller) which enable high speed data transfer
from a memory to a memory without use of the CPU.
The DMAC initiates the data transfer with an interrupt factor speci-
fied by the DMAC channel x (x = 0, 1) hardware transfer request
source bit (DxCEN), or with a software trigger.
The DxTMS [DMA Channel x (x = 0, 1) Transfer Mode Selection
Bit] selects one of two transfer modes; cycle steal mode or burst
transfer mode. In the cycle steal mode, the DMAC transfers one
byte of data for each request. In the burst transfer mode, the
DMAC transfers the number of bytes data specified by the transfer
count register for each request. The count register is a 16-bit
counter; the maximum number of data is 65,536 bytes per one re-
quest.
Figure 31 shows the DMA control block diagram and Figure 32
shows the structure of DMAC related registers.
[DMAC Index and Status Register] DMAIS
The DMAC Index and Status Register consists of various control
bits for the DMAC and its status flags.
The DMA Channel Index Bit (DCI) selects which channel ( 0 or 1)
will be accessed, since the mode registers, source registers, des-
tination registers and transfer count register of both DMAC
channels share the same SFR addresses, respectively.
[DMAC Channel x (x = 0, 1) Mode Registers 1, 2] DMAxM1,
DMAxM2
The 16 bits of DMAC Channel x Mode Registers 1 and 2 control
each operation of DMAC channels 0 and 1.
When the DMAC Channel x (x = 0, 1) Write Bit (DxDWC) is “0”,
data is simultaneously written into each latch and register of the
Source Registers, Destination Register, and Transfer Count Reg-
isters. When this bit is “1”, data is written only into their latches.
When data is read from each register, it must be read from the
higher bytes first, then the lower bytes. When writing data, write to
the lower bytes first, then the higher bytes.
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Interrupt
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UART2 receive, UART2 transmit,
INT
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, Timer 1, Timer X, CNTR
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Signal
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OBE
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(data),
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP (endpoint) 4 receive/transmit
EP1OUT FIFO data existing
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Case of DMAC
channel 1
DMAC channel X
Channel X timing
generator
Channel X transfer
source register
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Channel X transfer count register
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DxCEN
DxCRR
DxUMIE
DxHRS2
DxHRS1
DxHRS0
DxSRCE
DxSRID
DxRLD
DRLDD
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Temporary register
Index status register
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DxDAUE
Mode 1
register
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Channel X transfer
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Channel X transfer count latch
DxDWC
DxDWC
DxDWC
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