24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
TIMERS
The 7513 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00
16
”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 19 Timer block diagram
CNTR
active
edge switch bit
T
s
i
m
e
e
c
r
t
i
1
o
n
c
o
b
u
i
“
0
n
t
s
o
u
r
c
e
l
e
t
R
c
e
o
a
n
l
r
t
o
i
m
l
e
i
p
o
“
0
r
t
t
b
t
”
“
1
”
P5
5
/CNTR
1
“
0
”
C
e
N
d
T
e
R
1
s
a
i
c
t
c
t
i
h
v
e
b
g
w
i
t
“
10
”
T
c
i
m
o
e
t
r
r
o
Y
l
s
i
t
o
p
n
b
t
F
a
l
l
i
n
g
e
d
g
e
d
e
t
e
c
t
i
o
n
Period
Timer Y
interrupt
request
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
l
y
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Rising edge detection
“
00
”
,
“
01
”
,
“
11
”
T
m
i
m
o
e
e
r
Y
b
t
o
p
e
r
a
t
i
n
g
d
i
T
n
r
e
i
i
t
e
r
u
r
u
e
X
p
s
e
q
r
t
t
Timer X mode register
write signal
P5
4
/CNTR
0
Q
Q
T
S
P5
4
direction register
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
P5
4
latch
Timer X stop
control bit
“
0
”
“
1
”
T
c
i
m
o
e
t
r
r
o
X
l
w
i
t
r
i
t
e
n
b
Q
D
L
a
t
c
h
Q
D
L
a
t
c
h
“
1
”
“
0
”
“
1
”
“
1
0
”
T
i
n
“
0
i
m
g
0
e
m
”
,
r
o
0
X
d
1
e
”
o
p
b
“
1
e
i
1
r
s
”
a
t
-
t
“
,
f(
(
X
I
f
(
N
)
/
N
)
1
6
/
X
CI
N
e
d
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
*
)
Pulse width
measurement
mode
C
T
e
R
0
s
a
i
c
t
c
t
i
h
v
e
b
g
w
i
t
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
Q
Q
T
S
”
P
4
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
4
3
l
a
t
c
h
“
1
”
T
output
active edge
switch bit
Timer 2 write
control bit
“
0
”
“
1
”
T
output
control bit
“
1
”
P4
3
/
φ
/T
OUT
X
CIN
T
s
i
m
o
e
r
r
3
s
c
e
o
l
u
e
n
c
t
i
u
c
e
t
o
n
b
i
t
“
0
”
“
1
”
T
n
r
e
i
i
t
e
r
u
r
u
e
2
p
s
t
e
q
r
t
Timer 3
interrupt
request
T
s
i
m
e
e
c
r
t
i
2
o
n
c
o
b
u
i
n
t
s
o
u
r
c
e
l
e
t
Timer 1
interrupt
request
D
a
t
a
b
u
s
f(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
*
)
CNTR
0
interrupt
request
T
i
m
e
r
Y
o
p
e
r
a
t
i
0
n
0
g
”
,
m
“
0
o
1
d
”
e
,
“
1
b
0
i
t
”
“
“
1
1
”
R
c
e
o
a
n
l
r
t
o
i
m
l
e
i
p
o
“
1
r
t
t
b
t
”
P5
2
latch
e
p
o
r
b
i
t
“
1
R
c
e
o
a
n
l
r
t
o
i
m
l
t
t
”
P
5
3
l
a
t
c
h
Timer Y (low) (8)
T
i
m
e
r
Y
(
h
i
g
h
)
(
8
)
Timer 3 latch (8)
Timer 3 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Timer X (low) (8)
Timer X (high) (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
T
i
m
e
r
Y
(
l
o
w
)
l
a
t
c
h
(
8
)
T
i
m
e
r
Y
(
h
i
g
h
)
l
a
t
c
h
(
8
)
T
O
c
o
U
n
T
t
r
o
o
u
l
t
p
i
u
t
b
t
“
0
”
“
0
”
“
0
”
P
5
2
5
2
P
5
3
P
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P5
3
direction register
P
5
2
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
5
3
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
f(
(
f
X
(
I
N
)
/
N
)
1
6
/
X
CI
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
*
)
f(
(
f
X
(
I
N
)
/
N
)
1
6
/
X
CI
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
*
)
f(XIN)/16
(
f(X
CIN
)/16 in low-speed mode*
)
C
n
r
e
i
T
r
u
R
1
r
u
e
t
q
e
p
s
t
t
*
φ
= X
CIN
divided by 2 in low-speed mode