- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360515 > 7513 7513 Group Datasheet Datasheet 1067K/FEB.06.01 PDF資料下載
參數(shù)資料
| 型號： | 7513 |
| 英文描述： | 7513 Group Datasheet Datasheet 1067K/FEB.06.01 |
| 中文描述： | 7513組數(shù)據(jù)表數(shù)據(jù)表1067K/FEB.06.01 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | 7513 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an in-
terrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable
flag is “0”. Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software. The BRK instruction interrupt and reset cannot be
disabled with any flag or bit. The I flag disables all interrupts ex-
cept the BRK instruction interrupt and reset. If several interrupts
requests occurs at the same time, the interrupt with highest prior-
ity is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
I
Notes
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A
16
)
Timer X mode register (address 27
16
)
Timer Y mode register (address 28
16
)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control register (address 0031
16
)
Notes1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 8 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At detection of either rising or
falling edge of INT
2
input
At completion of serial I/O2 data
transmission or reception
At falling of conjunction of input
level for port P2 (at input mode)
At either rising or falling edge of
ADT input
Interrupt Source
Low
FFFC
16
FFFA
16
High
FFFD
16
FFFB
16
Priority
Vector Addresses
(Note 1)
Reset
(Note 2)
INT
0
INT
1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
0
CNTR
1
Timer 1
INT
2
Serial I/O2
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(valid at falling)
External interrupt (Valid when ADT
interrupt is selected
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 75160-101-36 | STIFTLEISTE ABTRENNBAR 1REIHIG 36POL |
| 75160-102-36 | STIFTLEISTE ABTRENNBAR 1REIHIG 36POL |
| 75160-105-36 | STIFTLEISTE ABTRENNBAR 1REIHIG 36POL |
| 75160-301-36 | STIFTLEISTE ABTRENNBAR 1REIHIG 36POL |
| 75160-302-36 | STIFTLEISTE ABTRENNBAR 1REIHIG 36POL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 75-130 | 制造商:Zierick Manufacturing Corporation 功能描述: |
| 75130-1213 | 制造商:MOLEX 功能描述: |
| 75-130477-52S | 功能描述:Circular Connector 制造商:amphenol industrial operations 系列:- 包裝:- 零件狀態(tài):有效 連接器類型:- 針腳數(shù):- 外殼尺寸 - 插件:- 外殼尺寸，MIL:- 安裝類型:- 端接:- 緊固類型:- 朝向:- 侵入防護(hù):- 外殼材料，鍍層:- 觸頭鍍層:- 特性:- 觸頭鍍層厚度:- 額定電流:- 電壓 - 額定:- 工作溫度:- 標(biāo)準(zhǔn)包裝:1 |
| 75-131018-1G | 制造商:Amphenol Corporation 功能描述:75-131018-01G - Bulk |
| 75-131018-1I | 制造商:Amphenol Corporation 功能描述:75-131018-01I - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。