13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7513 Group
Fig. 10 Memory map of special function register (SFR)
0003
16
0004
16
0
0006
16
0
0
0
0
0
0
0
0
0
0010
16
1
0012
16
1
0014
16
1
0016
16
1
0018
16
1
001A
16
001B
16
1
1
001E
16
1
0
0
0
0
0
0
0
1
1
1
2
1
6
6
6
0
5
1
6
0
0
0
0
0
0
0
0
0
7
1
8
1
9
1
A
1
B
1
C
1
D
1
E
1
F
1
6
6
6
6
6
6
6
6
6
0
1
1
6
0
3
1
6
0
5
1
6
0
7
1
6
0
9
1
6
0
0
C
1
D
1
6
6
0
F
1
6
P
P
o
o
r
r
t
t
P
P
0
0
(
d
P
i
0
r
e
)
c
P
Port P1 output control register (P1D)
P
r
t
P
2
(
P
2
)
P
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
P
r
t
P
3
(
P
3
)
P
r
t
P
3
o
u
t
p
u
t
c
o
n
o
r
t
P
1
(
P
1
)
o
o
o
o
g
i
s
t
e
r
(
P
2
D
)
P
Port P4 direction register (P4D)
P
r
t
P
5
(
P
5
)
Port P5 direction register (P5D)
P
r
t
P
6
(
P
6
)
Port P6 direction register (P6D)
P
r
t
P
7
(
P
7
)
Port P7 direction register (P7D)
o
r
t
P
4
(
P
4
)
o
o
o
Serial I/O1 status register (SIO1STS)
S
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
R
s
e
r
v
e
d
a
r
e
a
S
r
i
a
l
I
/
O
2
r
e
g
i
s
t
e
r
e
r
e
g
i
s
t
e
r
(
S
I
O
1
C
O
N
)
PULL register A (PULLA)
PULL register B (PULLB)
T
a
n
s
m
i
t
/
R
e
c
r
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r(TB/RB)
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
t
r
o
l
r
e
g
i
s
t
e
r
(
P
3
C
)
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
K
I
C
)
e
e
(
S
I
O
2
)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
2
002C
16
002D
16
2
2
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
3
3
0
B
1
6
0
0
E
1
F
1
6
6
0
0
E
1
F
1
6
6
Interrupt control register 2 (ICON2)
Timer 3 (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
T
e
r
1
2
3
m
o
d
T
O
U
o
u
t
p
u
t
c
P
M
c
o
n
t
r
o
l
r
e
PWM prescaler (PREPWM)
P
M
r
e
g
i
s
t
e
r
(
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Timer X (low) (TXL)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Timer 1 (T1)
Timer 2 (T2)
i
W
m
e
o
g
n
i
r
e
t
r
s
g
o
t
e
i
l
r
s
t
e
(
P
e
r
i
(
s
T
t
M
1
e
2
r
C
3
(
C
O
M
K
N
)
T
/
φ
r
g
W
O
)
U
T
)
Segment output enable register (SEG)
LCD mode register (LM)
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
A
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
D
A
1
c
o
n
v
e
r
s
i
o
n
r
e
g
i
D
A
2
c
o
n
v
e
r
s
i
o
n
r
e
g
i
D-A control register (DACON)
Watchdog timer control register (WDTCON)
W
P
W
M
)
-
-
-
t
s
s
e
t
r
e
t
e
(
r
r
h
(
i
D
(
D
g
h
A
A
-
1
2
o
r
d
e
r
)
(
A
D
H
)
)
)