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| 型號(hào)： | 71V2556S100PFG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, GREEN, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556S100PFG8 |
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6.42
16
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
NOTES:
1.
D
(A
1)
represents
the
first
input
to
the
external
address
A
1.
D
(A
2)
represents
the
first
input
to
the
external
address
A
2;
D
(A
2+1
)represents
the
next
input
data
in
the
burst
sequence
of
the
base
address
A
2,
etc.
where
address
bits
A
0and
A
1are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE2
is
HIGH.
3.
Burst
ends
when
new
address
and
control
are
loaded
into
the
SRAM
by
sampling
ADV/
LD
LOW.
4.
R
/W
is
don't
care
when
the
SRAM
is
bursting
(ADV/
LD
sampled
HIGH).
The
nature
of
the
burst
access
(Read
or
Write)
is
fixed
by
the
state
of
the
R/
W
signal
when
new
address
and
control
are
loaded
into
the
SRAM.
5.
Individual
Byte
Write
signals
(BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
two
cycles
before
the
actual
data
is
presented
to
the
SRAM.
Timing Waveform of Write Cycles(1,2,3,4,5)
tHE
tSE
R
/W
A
1
A
2
CLK
C
E
N
ADV/
L
D
ADDRESS
O
E
DATA
IN
tHD
tSD
tCH
tCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst
Pipeline
Write
Pipeline
Write
Pipeline
Write
tHB
tSB
(Burst
Wraps
around
to
initial
state)
tHD
tSD
(CEN
high,
eliminates
current
L-H
clock
edge)
(2)
D(
A2+2
)
D(
A2+3
)
D(A
1
)
D(A
2
)
D(A
2
)
4875
drw
07
B
W
1
-
B
W
4
C
E
1,
C
E
2
D(A
2+1
)
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