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參數(shù)資料
| 型號(hào)： | 71V2556S100PFG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, GREEN, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 7/23頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556S100PFG8 |
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6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
15
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
Q
(A
2)
represents
the
first
output
from
the
external
address
A
2;
Q
(A
2+1
)represents
the
next
output
data
in
the
burst
sequence
of
the
base
address
A
2,
etc.
where
address
bits
A0
and
A1
are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
2.
C
E
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Burst
ends
when
new
address
and
control
are
loaded
into
the
SRAM
by
sampling
ADV/
LD
LOW.
4.
R
/W
is
don't
care
when
the
SRAM
is
bursting
(ADV/
LD
sampled
HIGH).
The
nature
of
the
burst
access
(Read
or
Write)
is
fixed
by
the
state
of
the
R/
W
signal
when
new
address
and
control
are
loaded
into
the
SRAM.
ADV/
LD
(CEN
high,
eliminates
current
L-H
clock
edge)
O2(A2)
tCD
tHADV
Pipeline
Read
(Burst
Wraps
around
to
initial
state)
tCDC
tCLZ
tCHZ
tCD
tCDC
R/
W
CLK
CEN
ADDRESS
OE
DATA
OUT
tHE
tSE
A1
A2
O1(A2)
tCH
tCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst
Pipeline
Read
Pipeline
Read
BW
1
-
BW
4
4875
drw
06
CE
1
,
CE
2
(2)
Q(A
2+3
)
Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
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相關(guān)代理商/技術(shù)參數(shù) |
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| 71V2556S100PFGI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| 71V2556S133BG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Integrated Device Technology Inc 功能描述: |
| 71V2556S133BG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4.2ns 119-Pin BGA T/R |
| 71V2556S133PFG | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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