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參數(shù)資料
| 型號(hào)： | 71V2556S100PFG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, GREEN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556S100PFG8 |
6.42
20
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs(1)/
TDI/TMS
Device Outputs(2)/
TDO
TRST(3)
tJCD
tJDC
tJRST
tJS
tJH
tJCYC
tJRSR
tJF
tJCL
tJR
tJCH
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NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
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