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參數(shù)資料
| 型號(hào)： | 70824L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 70824L35PFI |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
17
Waveform of Write Cycles: Sequential Port
NOTES:
1. If
SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If
CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following
SLD even if CNTEN is LOW.
4. If SR/
W = VIL, data would be written to D0 again since CNTEN = VIH.
5.
SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
Waveform of Burst Write Cycles: Sequential Port
SLD
CNTEN
tCYC
SR/
W
SCE
SOE
SCLK
tCH
tCL
tDS
tDH
tOHZ
tEH
tES
(3)
(1)
tEH
tES
Dx
A0
D0
HIGH IMPEDANCE
tWS
tWH
tWS
tWH
tCD
tCKLZ
tWS
tWH
tWS
tWH
tCKHZ
D0
tDS
tDH
(4)
(5)
tEH
tES
D1
tDS
tDH
HIGH IMPEDANCE
SI/OIN
SI/OOUT
3099 drw 20
(4)
SLD
CNTEN
D2
SR/
W
SCLK
tCYC
tCH
tCL
tDS
tDH
tEH
tES
tEH
tES
(1)
(3)
A0
Dx
HIGH IMPEDANCE
tWS
tWH
tWS
tWH
tCKLZ
tWS
tWH
tWS
tWH
D1
D0
D2
tDS
tDH
tCD
SCE
SOE
(2)
SI/OIN
SI/OOUT
3099 drw 21
(5)
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