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參數(shù)資料
| 型號(hào)： | 70824L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 20/21頁(yè) |
| 文件大小： | 191K |
| 代理商： | 70824L35PFI |
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IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table: Sequential Address Pointer Operations(1,2,3,4,5)
Sequential Load of Address into Pointer/Counter(1)
NOTE:
1. "H" = VIH and "L" = VIL for the SI/O intput state.
NOTE:
1. At SCLK edge (A), SI/O0-SI/O11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A),
SSTRT1 and SSTRT2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B),
SLD and SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge
(B), while data will not be ready at edge (B) when
SLD is used, but will be ready at edge (C).
SLD
Mode(1)
Address Pointer Load Control (SLD)
In
SLDmode,thereisaninternaldelayofonecyclebeforetheaddress
pointer changes in the cycle following
SLD. When SLD is LOW, data on
the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-
HIGHtransitionofSCLK.Onthecyclefollowing
SLD,theaddresspointer
changestotheaddresslocationcontainedinthedata-inregister.
SSTRT1,
SSTRT2 may not be low whileSLD is LOW, or during the cycle following
SLD.TheSSTRT1andSSTRT2requireonlyoneclockcycle,sincethese
addresses are pre-loaded in the registers already.
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2.
RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3.
CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control).
CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When
SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
during the two cycles.
6.
SOE may be LOW with SCE deselect or in the write mode using SR/W.
Inputs/Outputs
MODE
SCLK
SLD
SSTRT1
SOE
↑
H
L
H
X
Non-Counter Advanced Sequential Write, without
EOB1 or EOB2 reached.
↑
H
L
X
Counter Advanced Sequential Write with
EOB1 and EOB2 reached.
↑
LH
H
(6)
No Write or Read due to Sequential port Deselect. No counter advance.
3099 tbl 14
SLD
SCLK
SI/O0-11
SSTRT(1 or 2)
A
B
ADDRIN
3099 drw 08
C
DATAOUT
(1)
15
MSB
LSB SI/O BITS
3099 drw 09
H
11 --------------------------------------------------------------------------------------------------
Address Loaded into Pointer
0
14
13
H
L
12
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