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參數(shù)資料
| 型號(hào)： | 70824L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 70824L35PFI |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
9
Case 5: Buffer Flow Modes
WithintheSARAM,theusercandesignateoneoftwobufferflowmodes
for each buffer. Each buffer flow mode defines a unique set of actions for
the sequential port address pointer and
EOB flags.InBUFFERCHAIN-
ING mode, after the address pointer reaches the end of the buffer, it sets
the corresponding
EOB flag and continues from the start address of the
otherbuffer.InSTOPmode,theaddresspointerstopsincrementingafter
itreachestheendofthebuffer.Thereisnolinearormaskmodeavailable.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
alsoallowsreadingandclearingthestatusofthe
EOBflags.Sevendifferent
CMD cases are available depending on the conditions of A0-A2 and R/
W. Address bits A3-A11and data I/O bits I/O12-I/O15are not used during
thisoperation.
Reset (RST)
Setting
RSTLOWresetsthecontrolstateoftheSARAM.RSTfunctions
asynchronously of SCLK (i.e. not registered). The default states after a
reset operation are displayed in the adjacent chart.
NOTE:
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
Buffer Command Mode (CMD)
Buffer Command Mode (
CMD) allows the random access port to
control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0-
I/O11 areusedtoaccessthestartofbufferandtheendofbufferaddresses
andtosettheflowcontrolmodeofeachbuffer.TheBufferCommandMode
Random Access Port CMD Mode(1)
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state.
2. A write into the buffer occurs when R/
W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and
CE = VIH.
NOTE:
1. R/
W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Register
Contents
Address
0
EOB Flags
Cleared to HIGH state
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0 (1)
End Address Buffer #1
4095 (4K)
Start Address Buffer #2
(1)
Cleared (set at invalid points)
End Address Buffer #2(1)
Cleared (set at invalid points)
Registered State
SCE = VIH, SR/W = VIL
3099 tbl 15
Case #
A2-A0
R/
W
DESCRIPTIONS
1
000
0 (1)
Write (read) the start address of Buffer #1 through I/O0-I/O11.
2
001
0 (1)
Write (read) the end address of Buffer #1 through I/O0-I/O11.
3
010
0 (1)
Write (read) the start address of Buffer #2 through I/O0-I/O11.
4
011
0 (1)
Write (read) the end address of Buffer #2 through I/O0-I/O11.
5
100
0 (1)
Write (read) flow control register.
6
101
0
Write only - clear
EOB1 and/or EOB2 flag.
7
101
1
Read only - flag status register.
8
110/111
(X)
(Reserved)
3099 tbl 16
15
MSB
LSB I/O BITS
3099 drw 10
H
11 --------------------------------------------------------------------------------------------------
Address Loaded into Buffer
0
14
13
H
L
12
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