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參數(shù)資料
| 型號(hào)： | 70824L35PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 10/21頁(yè) |
| 文件大小： | 191K |
| 代理商： | 70824L35PFI |
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18
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
NOTES: (Also used in Figure "Read
STRT/EOB Flag Timing")
1. If
SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If
CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3.
SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If
SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike
SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/
W = VIL, data would be written to D0 again since CNTEN = VIH.
6.
SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
SSTRT1/2
CNTEN
D3
SR/
W
SCE
SOE
SCLK
tCH
tCL
tEH
tES
tEH
tES
(4)
(1)
(3)
Dx
HIGH IMPEDANCE
tWS
tWH
tWS
tWH
tCKLZ
tWS
tWH
tWS
tWH
(2)
D2
D1
D3
tDS
tDH
tCD
(6)
HIGH IMPEDANCE
D0
EOB1/2
tEB
SI/OIN
SI/OOUT
3099 drw 22
(5)
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