參數(shù)資料
型號: 5962R9581901QQX
廠商: INTERSIL CORP
元件分類: 微控制器/微處理器
英文描述: 24 I/O, PIA-GENERAL PURPOSE, CDIP40
封裝: SIDE BRAZED, CERAMIC, DIP-40
文件頁數(shù): 15/17頁
文件大小: 232K
代理商: 5962R9581901QQX
7
Operational Description
Control Word
The data direction and mode of Ports A, B and C are
determined by the contents of the Control Word. See
Figure 11. The Control Word can be both written and read as
shown in Table 1 and 2. During write operations, the function
of the Control Word being written is determined by data bit
D7. If D7 is low, the data on D0 - D3 will set or reset one of
the bits of Port C. See Figure 12. During read Operations,
the Control Word will always be in the format illustrated in
Figure 11 with Bit D7 high to indicate Control Word Mode
Information.
Port C
One 8-bit data output latch/buffer and one 8-bit data input
buffer (no latch for input). This port can be divided into two
4-bit ports under the mode control. Each 4-bit port contains
a 4-bit latch and can be used for the control signal outputs
and status signal inputs in conjunction with Ports A and B.
See Figure 9B.
FIGURE 9A.
FIGURE 9B.
FIGURE 9. I/O PORT CONFIGURATION
MASTER
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
WR
SIGNAL
RD
CONTROL
EXTERNAL
PORT A PIN
MASTER
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
WR
SIGNAL
EXTERNAL
PORT B, C
P
VDD
PIN
TABLE 1.
A1
A0
RD
WR
CS
INPUT OPERATION
(READ)
00010
Port A - Data Bus
01010
Port B - Data Bus
10010
Port C - Data Bus
11010
Control Word - Data Bus
TABLE 2.
A1
A0
RD
WR
CS
OUTPUT OPERATION
(WRITE)
00100
Data Bus - Port A
01100
Data Bus - Port B
10100
Data Bus - Port C
11100
Data Bus - Control Word
TABLE 3.
A1
A0
RD
WR
CS
DISABLE FUNCTION
XXXX
1
Data Bus - 3-State
RD, WR
D7 - D0
A0 - A1
BCA
CS
8
4
8
4
I/O
PB7 - PB0 PC3 - PC0 PC7 - PC4 PA7 - PA0
MODE 0
DATA BUS
CONTROL BUS
ADDRESS BUS
BCA
8
I/O
PB7 - PB0
PA7 - PA0
MODE 1
CONTROL
OR I/O
CONTROL
OR I/O
BCA
8
I/O
BIDIREC-
PB7 - PB0
PA7 - PA0
MODE 2
I/O
CONTROL
TIONAL
FIGURE 10. BASIC MODE DEFINITIONS AND BUS INTERFACE
HS-82C55ARH
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