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參數(shù)資料
| 型號： | 5962R9581901QQX |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 232K |
| 代理商： | 5962R9581901QQX |
4
Waveforms
FIGURE 1. MODE 0 (BASIC INPUT)
FIGURE 2. MODE 0 (BASIC OUTPUT)
FIGURE 3. MODE 1 (STROBED INPUT)
FIGURE 4. MODE 1 (STROBED OUTPUT)
FIGURE 5. MODE 2 (BIDIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB
occurs before RD is permissible.
FIGURE 6. WRITE TIMING
FIGURE 7. READ TIMING
RD
INPUT
CS, A1, A0
D7 - D0
TPVRL
TRHPX
TRLRH
TAVRL
TRHAX
TRLDV
TRHDZ
WR
D7 - D0
CS, A1, A0
OUTPUT
TWLWH
TDVWH
TWHDX
TAVWL
TWHPV
TWHAX
STB
IBF
INTR
RD
INPUT FROM
PERIPHERAL
TSLSH
TSLIH
TSHPX
TPVSH
TRHIL
TRLNL
TSHNH
WR
OBF
INTR
ACK
OUTPUT
TWLNL
TWHOL
TKLOH
TWHPV
TKLKH
TKHNH
WR
OBF
INTR
ACK
STB
IBF
PERIPHERAL
BUS
RD
DATA FROM CPU
TO HS-82C55ARH
TWHOL
TSLIH
TKLOH
TKLKH
DATA FROM PERI-
PHERAL TO
DATA FROM
HS-82C55ARH
TO PERIPHERAL
DATA FROM
HS-82C55ARH
TO CPU
TSLSH
TKLPV
TKHPX
TPVSH
TSHPX
TRHIL
A0 - A1, CS
DATA BUS
WR
TAVWL
TWHAX
TWLWH
TWHDX
TDVWH
A0 - A1, CS
RD
DATA BUS
TAVRL
TRHAX
HIGH IMPEDANCE
VALID
HIGH IMPEDANCE
TRLRH
TAVRL
TRHDX
HS-82C55ARH
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