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參數(shù)資料
| 型號： | 5962R9581901QQX |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 232K |
| 代理商： | 5962R9581901QQX |
2
Pin Descriptions
SYMBOL
PIN
NUMBERS
TYPE
DESCRIPTION
PA0-7
1-4, 37-40
I/O
Port A: General purpose I/O Port. Data direction and mode is determined by the contents of the
Control Word.
PB0-7
18-25
I/O
Port B: General purpose I/O port. See Port A.
PC0-3
14-17
I/O
Port C (Lower): Combination I/O port and control port associated with Port B. See Port A.
PC4-7
10-13
I/O
Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A.
D0-7
27-34
I/O
Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are low and
as an output when CS and RD are low.
VDD
26
I
VDD: The +5V power supply pin. A 0.1
F capacitor between pins 26 and 7 is recommended for
decoupling.
GND
7
I
Ground.
CS
6
I
Chip Select: A “l(fā)ow” on this input pin enables the communication between the HS-82C55ARH
and the CPU.
RD
5
I
Read: A “l(fā)ow” on this input pin enables the HS-82C55ARH to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to “read from” the HS-82C55ARH.
WR
36
I
Write: A “l(fā)ow” on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
A0 and A1
8, 9
I
Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs,
control the selection of one of the three ports or the control word registers. They are normally
connected to the Least Significant Bits of the address bus (A0 and A1).
Reset
35
I
Reset: A “high” on this input clears the control register and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs to a logic “1”
state with a maximum hold current of 400
A.
HS-82C55ARH
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