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參數(shù)資料
| 型號： | 5962F9855202QXA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 35/64頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | 5962F9855202QXA |
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40
118
D2
TTO
OPERAND DATA BUS ARBITRATION
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
119
120
E3
C1
TUI
Bus Request. The UT69R000 asserts this signal to indicate
it is requesting control of the Operand data bus (D0 - D15).
BRQ enters a high-impedance state when the UT69R000
is in the test mode (TEST = 0).
Bus Grant. When asserted, this signal indicates the
UT69R000 may take control of the Operand data bus. It is
tied to an internal pull-up resistor.
Bus Busy. A bus master asserts this input to inform the
UT69R000 that another bus master is using the Operand
data bus. It is tied to an internal pull-up resistor.
OPERAND DATA BUS CONTROL
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
121
112
E2
B3
TUI
TTO
Data Transfer Acknowledge. This signal tells the
UT69R000 that a data transfer has been acknowledged
and the UT69R000 can complete the bus cycle. To
assure the UT69R000 operates with no wait states,
DTACK can be tied low. DTACK is tied to an internal
pull-up resistor.
Memory or I/O. Indicates whether the current bus cycle
is for memory (high) or I/O (low). It remains in the high-
impedance state during bus cycles when the UT69R000
does not control the Operand buses.
AL
117
B1
TTO
AL
Bus Grant Acknowledge Output. The UT69R000 asserts
this signal to indicate it is the current bus master. When
low, BGACK inhibits other devices from becoming the
bus master. When the UT69R000 relinquishes control of
the bus, BGACK enters a high-impedance state.
114
C4
TTO
Read/Write. Indicates the direction of data flow with
respect to the UT69R000. R/WR high means the
UT69R000 is attempting to read data from an external
device, and R/WR low means the UT69R000 is
attempting to write data to an external device. R/WR
remains in a high-impedance state when the UT69R000
does not control the Operand buses.
Continued on page 41.
--
BRQ
BGNT
BUSY
BGACK
DTACK
M/IO
R/WR
相關PDF資料 |
PDF描述 |
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| 5962G9855201QXX | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962G9855202VXA | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962G9855202VXX | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962H9855201VXC | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962H9855202QXX | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
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