參數(shù)資料
型號(hào)： 5962F9855202QXA
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
封裝： CERAMIC, PGA-144
文件頁(yè)數(shù)： 11/64頁(yè)
文件大小： 1464K
代理商： 5962F9855202QXA
19
Executing the LRI instruction begins when the falling edge of
OSCIN signals the start of time period CK1. At the beginning
of CK1, the data previously stored in the ACC becomes a valid
address on the instruction port address bus (RA(19:0)) and
STATE1 output becomes active indicating the UT69R000 is
executing an instruction.
The data on the data bus is read into the UT69R000 during time
period CK2. The function of the remainder of the bus cycle
(time periods CK3 and CK4) is the same as for other
instructions. STATE1 is high, indicating the next instruction is
being fetched from memory and is ready for execution during
the next bus cycle.
4.0 Operand Port
The UT69R000 Operand Data bus interface supports multiple
processor and direct memory access (DMA) configurations.
The Operand Address bus A(15:0), data bus D(15:0), and
memory control bus signals (DS, R/WR, and M/IO) are TTL-
compatible outputs that may be placed in a high-impedance
state. These signals are only active during bus cycles when the
UT69R000 is the current bus master. On other bus cycles, these
signals enter a high-impedance state so an alternate bus master
can control the port.
OSCIN
CK1
CK2
CK3
CK4
STATE1
Figure 17. Machine Cycle 3 (4 Clock Cycle Instructions)
EXECUTE
RA(19:0)
RD(15:0)
Note:
1. Examples of three clock cycle instructions include (long immediate accesses):
MOV Rd, FFFF (hex)
ADD Rd, FFFF (hex)
STATUS
DS
A(15:0)
D(15:0)
Address Valid
Data Read
Control Valid
Fetch Address Valid
Fetch Instruction
Immediate Address
Immediate Data
FETCH
Fetch Address Valid
Fetch Instruction
(M/IO, R/WR)
相關(guān)PDF資料
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5962G9855201QXX 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
5962G9855202VXA 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962G9855202VXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
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