參數(shù)資料
型號(hào)： 5962-9855201VXC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
封裝： CERAMIC, PGA-144
文件頁(yè)數(shù)： 64/64頁(yè)
文件大?。?/td> 1464K
代理商： 5962-9855201VXC
9
UART Transmitter Buffer Register
The UT69R000’s internal UART forms an 11-bit serial string
by combining a Start bit, the eight Data bits from the
Transmitter Buffer Register, an odd Parity bit, and a Stop bit.
Figure 9 shows the composition of the serial data string. The
UT69R000 transmits this serial string through the UARTOUT
pin at a rate of 9600 baud (TIMCLK = 12MHz).
The UT69R000’s internal UART has a double-buffered data
transmission register (figure 10). The UT69R000 first loads
the data for transmission into the Transmitter Buffer Register.
If the UART Transmitter Register is empty, data from the
Transmit Buffer Register automatically transfers to the UART
Transmitter Register. At this time, the TBE bit goes active
indicating more data may be loaded into the Transmit Buffer
Register. This double-buffering scheme allows contiguous
transmission of serial data streams and also decreases the
UT69R000’s required overhead for the UART interface. The
UT69R000 loads the 8-bit Transmit Buffer Register via the
OTR Rd, TXMT instruction.
Two status signals are associated with transmitting serial data.
These signals are the UART Transmitter Buffer Empty (TBE)
and UART Transmitter Register Empty (TE). TBE and TE are
both active high and provide information on the status of double
buffering the UART’s transmitted data. TBE and TE are read
from the System Status Register bits 2 and 1
respectively.
5
4
T3
R
2
01
S
T
D
7
T
X
D
T
X
D
T
X
6
T
X
D
T
X
D
T
X
D
T
X
D
T
X
D
P
A
S
T
O
Figure 9. UART Transmitter Data String
P
R
DIRECTION
OF DATA
FLOW OUT
OF THE
UT69R000
Figure 10. The UT69R000 UART Double-Buffered Transmitter Register
REGISTER (OTR) INSTRUCTION
TBR WITH AN OUTPUT
DATA IS LOADED INTO THE
OF THE SYSTEM STATUS
READ FROM BIT 1
TRANSMITTER REGISTER IS
STATUS OF THE UART
8
REGISTER
UART TRANSMITTER
REGISTER (TBR)
UART TRANSMITTER BUFFER
16
DATA BUS
THE UT69R000’s INTERNAL
FROM BIT 2
TBR IS READ
STATUS OF THE
DATA FLOW
DIRECTION OF
T
R
T
S
0
1
2
3
4
5
6
7
X
T
X
T
X
T
X
T
X
T
X
T
X
T
X
T
R
A
P
O
T
S
0
1
2
3
4
5
6
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
D
X
T
7
D
X
T
D
C
D
C
D
C
D
C
D
C
D
C
D
C
D
C
OF THE SYSTEM
REGISTER
STATUS REGISTER
相關(guān)PDF資料
PDF描述
5962-9855202QXC 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962-9855202QXX 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962F9855202QXA 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
5962G9855201QXX 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144
5962G9855202VXA 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144
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