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| 型號(hào)： | 5962-9855201VXC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | 5962-9855201VXC |
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21
After the UT69R000 recognizes the current bus cycle is
finished, DS becomes inactive (transition from low to high) on
the first rising edge of OSCIN after the end of time period CK4.
The bus cycle completely ends one full clock cycle after the
end of time period CK4, when BGACK, R/WR, and the
Operand Address and Data buses enter a high-impedance state.
4.2 DMS Operation and Bus Arbitration
Figure 22 shows the timing diagram of the signal relationships
for the UT69R000 during a DMA operation. For DMA
operations, multipurprocessor, and Operand bus arbitration
functions, the UT69R000 provides four active-low control
signals for managing the Operand bus and preventing bus
contention. These signals are Bus Request (BRQ, Bus Grant
(BGNT), Bus Busy (BUSY), and Bus Grant Acknowledge
(BGACK).
Each of the four bus control signals provides a specific function
for controlling Operand bus operation. The function of each
of the four signals is given below.
Bus Request (BRQ)
The UT69R000 generates BRQ to indicate a request to use the
Operand buses. The UT69R000 retains control of the buses by
keeping the BGACK signal active until it no longer requires
the buses.
Bus Grant (BGNT)
An external arbitrator generates this input indicating to the
UT69R000 that it has the highest priority. This informs the
UT69R000 to control the Operand buses as soon as the present
bus master relinquishes bus control by asserting BUSY.
Bus Busy (BUSY)
Another bus master generates BUSY input to the UT69R000,
indicating another bus master is using the bus.
Bus Grant Acknowledge (BGACK)
The UT69R000 generates this signal to indicate it is the present
bus master. BGACK enters a high-impedance state when the
UT69R000 gives up control of the Operand buses.
CK4
CK3
CK2
CK1
OSCIN
RISC
ADDRESS
RISC
DATA
ADDRESS VALID (ACC)
NEXT ADDRESS
LRI
DATA VALID (RSn)
NEXT
Figure 19. LRI Instruction Typical Timing
INSTRUCTION
STATE1
OE
WE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-9855202QXC | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962-9855202QXX | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962F9855202QXA | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962G9855201QXX | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 5962G9855202VXA | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CPGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-9855501VPA | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 QML Class V Prec Timer RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| 59629856401QEA | 制造商:TI 功能描述:SNJ5447AJ |
| 5962-9856401QEA | 制造商:Texas Instruments 功能描述:Decoder/Driver Single 4-to-7 16-Pin CDIP Tube |
| 5962-9858401QFA | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| 5962-9858501QFA | 功能描述:總線接收器 RoHS:否 制造商:Texas Instruments 接收機(jī)數(shù)量:4 接收機(jī)信號(hào)類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel |
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