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參數(shù)資料
| 型號： | 5962-9855201VXC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CPGA144 |
| 封裝： | CERAMIC, PGA-144 |
| 文件頁數(shù)： | 38/64頁 |
| 文件大小： | 1464K |
| 代理商： | 5962-9855201VXC |
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43
Memory Parity (Error). Asserting this input indicates a
machine error. Bit 13 of the UT69R000’s Fault
Register, is set when MCHNE2 is active. Under no
circumstances should MCHNE2 be tied in its active
state. It is tied to an internal pull-down resistor. Interrupt
is not cleared via software until the negation of the input
signal.
MCHNE1
125
G2
TUI
INTERRUPTS/EXCEPTIONS
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
122
D1
TUI
System Fault. This positive edge-triggered input sets bit 8
(MCHNE1) in the UT69R000’s Fault Register. Under no
circumstances should MCHNE1 be tied in its active state.
It is tied to an internal pull-up resistor. Interrupt is not
cleared via software until the negation of the input signal.
MCHNE2
Bus Time Error. It is asserted when a bus error or a timeout
occurs. During I/O bus cycles, an active BTERR sets bit
10 of the Fault Register. During Memory bus cycles, an
active BTERR sets bit 7 of the Fault Register. Under no
circumstances should BTERR be tied in its active state. It
is tied to an internal pull-up resistor. Interrupt is not cleared
via software until the negation of the input signal.
124
F2
TDI
MPROT
123
F3
TUI
AH
Memory Protect Fault. When asserted, it informs the
UT69R000 that a memory-protect fault has occurred on the
Operand Data Bus. An access fault, a write-protect fault, or
an execute-protect fault causes a memory-protect fault. If the
UT69R000 is using the bus and MPROT is asserted, bit 15
of the Fault Register (CPU Fault) is set. If the UT69R000 is
not using the bus and MPROT is asserted, bit 14 of the Fault
Register (DMA Error) is set. It is tied to an internal pull-up
resistor. Interrupt is not cleared via software until the
negation of the input signal.
AL
AH
56
M15
TUI
62
J15
User Interrupts. These interrupts are active on a negative-
going pulse and each will set, when active, its associated bit
in the Pending Interrupt Register. The interrupts are
maskable by setting the associated bits in the Interrupt Mask
Register. Asserting MRST resets all interrupts. They are
tied to an internal pull-up resistor.
57
58
59
60
K13
K14
J14
J13
63
H14
55
L14
TUI
AL
Power Fail (Interrupt). Asserting this input
informs the UT69R000 that a power failure has occurred and
the present process will be interrupted. This input sets bit 15
in the Pending Interrupt Register. A Power Fail Interrupt (bit
15) cannot be disabled or masked. It is tied to an internal pull-
up resistor.
47
R14
TUI
AL
Master Reset. This input initializes the UT69R000 to a
reset state. The UT69R000 must be reset after power
(Vcc) is within specification and stable to ensure proper
operation. The system must hold MRST active for at
least one period of SYSCLK to assure the UT69R000
will be reset. It is tied to an internal pull-up resistor.
AH
AL
BTERR
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT2
PFAIL
MRST
61
K15
TUI
--
NUI4
Not used input 4. Internal UTMC use only. Tie high.
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