參數(shù)資料
型號: 28F320B3
廠商: Intel Corp.
英文描述: SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述: 智能高級啟動3座4 - ,8 - ,16 - ,32 - Mbit閃存家庭
文件頁數(shù): 79/82頁
文件大小: 749K
代理商: 28F320B3
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
73
Table C9. Protection Register Information
(1)
Length
P = 39h
(P+E)h
Table C10. Burst Read Information
(1)
Table C11. Partition and Erase-block Region Information
Bottom
Top
(1)
(1)
Description
Hex
Code Value
--01
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
00h,
indicates that 256 protection fields are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0
15 point to the Protection register Lock
byte, the section
s first byte. The following bytes are factory
pre-programmed and user-programmable.
Add.
47:
1
1
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
48:
49:
4A:
4B:
--80
--00
--03
--03
80h
00h
8 byte
8 byte
bits 0
7 = Lock/bytes Jedec-plane physical low address
bits 8
15 = Lock/bytes Jedec-plane physical high address
bits 16
23 =
n
such that 2n = factory pre-programmed bytes
bits 24
31 =
n
such that 2n = user programmable bytes
Length
Description
Hex
Code Value
--03
P = 39h
(P+13)h
(Optional flash features and commands)
Page Mode Read capability
bits 0
7 =
n
such that 2
n
HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
Add.
4C:
1
8 byte
(P+14)h
1
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3
7 = Reserved
bits 0
2
n
such that 2
n+1
HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device
s burstable address
space. This field
s 3-bit value can be written directly to the
Read Configuration Register bits 0
2 if the device is
configured for its maximum word width. See offset 28h for
4D:
--03
3
(P+15)h
1
4E:
--01
4
(P+16)h
(P+17)h
1
1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
4F:
50:
--02
--07
8
Cont
See table below
Address
Len
Bot
1
51:
Description
P = 39h
(P+18)h
P = 39h
(P+18)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
(Optional flash features and commands)
Top
51:
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