參數資料
型號: 28F320B3
廠商: Intel Corp.
英文描述: SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述: 智能高級啟動3座4 - ,8 - ,16 - ,32 - Mbit閃存家庭
文件頁數: 21/82頁
文件大?。?/td> 749K
代理商: 28F320B3
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
15
n: # of Clock periods (rounded up to the next integer)
*
Must use LC = n - 1 when the starting address is
not
aligned to a four-word boundary and CR.3 =
1 (No Wrap).
NOTE:
1. The 16-word boundary is the end of device word-line.
Parameters defined by CPU
:
t
ADD-DELAY
= Clock to CE#, ADV#, or Address Valid whichever occurs last.
t
DATA
= Data set up to Clock.
Parameters defined by flash
:
t
AVQV
= Address to Output Delay.
Example:
CPU Clock Speed = 52 MHz
t
ADD-DELAY
= 6 ns (typical speed from CPU) (max)
t
DATA
= 4 ns (typical speed from CPU) (min)
t
AVQV
= 70 ns (from AC Characteristic - Read Only Operations Table)
From Eq. (1):
1/52 (MHz) = 19.2 ns
From Eq. (2)
n(19.2 ns)
70 ns + 6 ns + 4 ns
n(19.2 ns)
80 ns
n
80/19.2 = 4.17
=
5 (Integer)
From Eq. (3)
n - 2 = 5 - 2 = 3
First Access Latency Count Setting to the CR is Code 3.
(
Figure 6,
Data Output with LC Setting at Code 3
on page 16
displays example data)
Table 8. First Latency Count (LC)
LC Setting
Mode
Wrap
Aligned to 4-word
Boundary
Wait Asserted on 16-Word
Boundary Crossing
n-1
4 or 8
disabled
no
yes, occurs on every occurrence
n-2
4 or 8
disabled
yes
no
n-2
4 or 8
enabled
no
no
n-2
4 or 8
enabled
yes
no
n-1
continuous
X
X
yes, occurs once
Figure 5. Word Boundary
0
1
2
3
4
5
6
7
8
9
A
B C D E
F
16 Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
4 Word Boundary
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