參數(shù)資料
型號(hào): 28F320B3
廠商: Intel Corp.
英文描述: SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述: 智能高級(jí)啟動(dòng)3座4 - ,8 - ,16 - ,32 - Mbit閃存家庭
文件頁數(shù): 5/82頁
文件大?。?/td> 749K
代理商: 28F320B3
Preliminary
v
28F320W30, 28F3204W30, 28F6408W30, 28F640W30
Revision History
Date of
Revision
Version
Description
09/19/00
-001
Original Version
03/14/01
-002
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2,
Signal Descriptions (
DQ
15
0
, ADV#, WAIT, S-UB#, S-LB#, V
CCQ
)
Revised Section 3.1,
Bus Operations
Revised Table 5,
Command Bus Definitions
, Notes 1 and 2
Revised Section 4.2.2,
First Latency Count (LC
);
revised Figure 6,
Data Output
with LC Setting at Code 3
; added Figure 7,
First Access Latency Configuration
Revised Section 4.2.3,
WAIT Signal Polarity (WT)
Added Section 4.2.4,
WAIT Signal Function
Revised Section 4.2.5,
Data Output Configuration (DOC)
Added Figure 8,
Data Output Configuration with WAIT Signal Delay
Revised Table 13,
Status Register DWS and PWS Description
Revised entire Section 5.0,
Program and Erase Voltages
Revised entire Section 5.3,
Enhanced Factory Programming (EFP)
Revised entire Section 8.0,
Flash Security Modes
Revised entire Section 9.0,
Flash Protection Register
; added Table 15,
Simulta-
neous Operations Allowed with the Protection Register
Revised Section 10.1,
Power-Up/Down Characteristics
Revised Section 11.3,
DC Characteristics. C
hanged I
I
I
Specs from
18 μA to 21μA; changed I
CCR
Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20,
WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21,
WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22,
WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23,
Write Waveform
Revised Section 12.4,
Reset Operations
Clarified Section 13.2,
SRAM Write Operation
, Note 2
Revised Section 14.0,
Ordering Information
Minor text edits
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