參數(shù)資料
型號(hào)： 28F160C3
廠商： INTEL CORP
元件分類： DRAM
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 8M X 8 FLASH 3V PROM
文件頁(yè)數(shù)： 20/59頁(yè)
文件大小： 321K
代理商： 28F160C3
28F800C3, 28F160C3, 28F320C3
E
20
PRELIMINARY
3.3.5
READING A BLOCK’S LOCK STATUS
The lock status of every block can be read in the
configuration read mode of the device. To enter this
mode, write 90H to the device. Subsequent reads at
Block Address + 00002 will output the lock status of
that block. The lock status is represented by DQ
0
and DQ
1
. DQ
0
indicates the Block Lock/Unlock
status and is set by the Lock command and cleared
by the Unlock command. It is also automatically set
when entering Lock-Down. DQ
1
indicates Lock-
Down status and is set by the Lock-Down
command. It cannot be cleared by software, only by
device reset or power-down.
Table 8. Block Lock Status
Item
Address
Data
Block Lock Configuration
XX002
LOCK
Block Is Unlocked
DQ
0
= 0
Block Is Locked
DQ
0
= 1
Block Is Locked-Down
DQ
1
= 1
3.3.6
LOCKING OPERATIONS DURING
ERASE SUSPEND
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock, or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation,
first write the erase suspend command (B0H), then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired lock command sequence to a block and
the lock status will be changed. After completing
any desired lock, read, or program operations,
resume the erase operation with the Erase Resume
command (D0H).
If a block is locked or locked-down during a
suspended erase of the same block, the locking
status bits will be changed immediately, but when
the erase is resumed, the erase operation will
complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix A for detailed
information on which commands are valid during
erase suspend.
3.3.7
STATUS REGISTER ERROR
CHECKING
Using nested locking or program command
sequences during erase suspend can introduce
ambiguity into status register results.
Since locking changes are performed using a two
cycle command sequence, e.g., 60H followed by
01H to lock a block, following the Configuration
Setup command (60H) with an invalid command will
produce a lock command error (SR.4 and SR.5 will
be set to 1) in the status register. If a lock
command error occurs during an erase suspend,
SR.4 and SR.5 will be set to 1 and will remain at 1
after the erase is resumed. When erase is
complete, any possible error during the erase
cannot be detected via the status register because
of the previous locking command error.
A similar situation happens if an error occurs during
a program operation error nested within an erase
suspend.
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