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參數(shù)資料
| 型號： | 28F160C3 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器) |
| 中文描述： | 8M X 8 FLASH 3V PROM |
| 文件頁數(shù)： | 11/59頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 28F160C3 |
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E
3.0
28F800C3, 28F160C3, 28F320C3
11
PRELIMINARY
PRINCIPLES OF OPERATION
The 3 Volt Advanced+ Boot Block flash memory
family utilizes a CUI and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% CMOS-evel control inputs and
fixed
power
supplies
programming.
during
erasure
and
The internal WSM completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1
Bus Operation
The 3 Volt Advanced+ Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
3.1.1
READ
The flash memory has four read modes available:
read array, read configuration, read status and read
query. These modes are accessible independent of
the V
voltage. The appropriate read mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at V
IH
. Figure 8
illustrates a read cycle.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (V
), the device
outputs are disabled. Output pins are placed in a
high-mpedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (V
) places the device in standby mode,
which
substantially
reduces
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
device
power
Table 3. Bus Operations
(1)
Mode
Notes
RP#
CE#
OE#
WE#
DQ
0
–7
DQ
8–15
Read (Array, Status,
Configuration, or Query)
2,3,4
V
IH
V
IL
V
IL
V
IH
D
OUT
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
High Z
High Z
Standby
2
V
IH
V
IH
X
X
High Z
High Z
Reset
2,7
V
IL
X
X
X
High Z
High Z
Write
2,5,6,7
V
IH
V
IL
V
IH
V
IL
D
IN
D
IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
8-bit devices use only DQ [0:7], 16-bit devices use DQ [0:15]
X must be V
IL
, V
IH
for control pins and addresses.
See DC Characteristicsfor V
PPLK
, V
PP1
, V
PP2
, V
PP3
, voltages.
Manufacturer and device codes may also be accessed in read configuration mode (A
1
–A
20
= 0). See Table 4.
Refer to Table 5 for valid D
IN
during a write operation.
To program or erase the lockable blocks, hold WP# at V
IH
.
RP# must be at GND
±
0.2 V to meet the maximum deep power-down current specified.
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