240
13.0 RS8234 Registers
13.7 PCI Bus Interface Registers
RS8234
Datasheet for RS8234 xBR ServiceSAR
N8234DS1B
MAX_LATENCY
This read-only register specifies how often the RS8234 device needs to gain access to the PCI bus,
assuming a clock rate of 33 MHz. Set to 0x02 (a period of time in units of 1/4 microseconds).
MIN_GRANT
This read-only register specifies how long of a burst period the RS8234 device needs to gain access to
the PCI bus. Set to 0x50 (a period of time in units of 1/4 microseconds).
INTERRUPT_PIN
This read-only register tells which interrupt pin the device (or device function) uses. Set to 0x01 (cor-
responds to interrupt pin INTA#).
INTERRUPT_LINE
Interrupt line identifier. The value in this register tells which input of the system interrupt controller(s)
the device’s interrupt pin is connected to. The device itself does not use this value; rather, it is used by
device drivers and operating systems.
SPECIAL_STATUS
_REGISTER
Device status not defined by the PCI specification. The field is further subdivided into subfields as
shown in
Table 13-45 below. Detailed descriptions of these subfields can be found in the PCI bus spec-
ification. Note that the configuration registers are accessed starting from byte address 0 in the config-
uration space allotted to an adapter card containing the SAR chip. Access to the configuration registers
is available only to the PCI host CPU, and is independent of all other SAR logic.
MASTER_READ
_ADDR
Current read target address used by PCI bus master (read only).
MASTER_WRITE
_ADDR
Current write target address used by PCI bus master (read only).
EEPROM_REGISTER
A 32-bit register controlling access to the I2C Serial EEPROM.
See Table 13-46 for a description of the
specific fields in the EEPROM_REGISTER.
PM_CAPABILITY
Power Management Capabilities register. A 16-bit read-only register which provides information on the
capabilities of the function related to Power Management. See the PCI Bus Power Management Inter-
face Specification Revision 1.0 for specific information related to this register.
NEXT_CAP_PTR
Next Item Pointer register. This field provides an offset into the PCI Configuration space pointing to the
location of the next item of the linked capability list. If there are no additional items in the Capabilities
List, this register is set to 0x00.
CAPABILITY_ID
Capability Identifier. When set to 0x01, indicates that the linked list item being pointed to is the PCI
Power Management registers. Default value is 0x01.
PM_DATA
Power Management Data register. This 8-bit read-only register provides a mechanism for the Power
Management function to report state-dependent operating data, such as power consumed or heat dis-
sipation. See the PCI Bus Power Management Interface Specification Revision 1.0 for specific informa-
tion related to this register.
PMCSR
Power Management Control/Status register. This 16-bit register is used to manage the PCI function’s
power management state, as well as to enable and monitor power management events. See the PCI
Bus Power Management Interface Specification Revision 1.0 for specific information related to this
register.
Table 13-43. PCI Command Register
Bit
Field
Size
Name
Description
15-10
6
Reserved
Set to 0x000.
9
1
FB_EN
Master Fast Back-to-back enable across target.
Table 13-42. PCI Configuration Registers Field Descriptions (2 of 2)
Field Name
Description/Function