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11.0 PCI Bus Interface
11.3 PCI Bus Master Logic
RS8234
Datasheet for RS8234 xBR ServiceSAR
N8234DS1B
11.3 PCI Bus Master Logic
The PCI bus master logic block is responsible for accepting read and write com-
mands from the DMA coprocessor (passed via the burst FIFO buffers), and in
turn acquiring mastership of the PCI bus and generating transactions to perform
the actual data transfers. The bus master logic contains the following:
A command decoder which interprets commands issued from the DMA
coprocessor.
A burst controller that counts off read and write cycles in each burst on the
PCI bus (and also latches and drives the address and command during the
address phase of each transfer).
Arbitration logic that acquires control of the PCI bus.
A bus state machine that sequences and controls transfers.
The bus master implements a software-configurable maximum burst length
counter. This counter is started at the beginning of each read or write burst trans-
action, and counts the actual number of words transferred during the burst. When
it reaches the value set in the MAX_BRST_LEN field of the PCI configuration
space, the burst is terminated and a new address phase is begun.
It is possible for the addressed slave to request a disconnect or a retry during a
read or a write transfer, using the defined PCI protocol sequence. In this case, the
bus master logic will terminate the current burst, maintain its bus request, and
restart the transfer at the point of termination. Disconnects and retries are not
regarded as errors.
Five possible sources of error are present during any PCI bus master transac-
tion. If the any of the following five errors occur, the bus master logic will perma-
nently terminate the transaction, flag an error, and cease to process any more
commands.
1
Target Abort—The PCI transaction will terminate if the addressed target
signals a target abort. In this case, the RTA and MERROR bits in the PCI
Configuration Register space will be set and the PCI_BUS_STATUS[4] bit
in the SYS_STAT Register will be set.
2
Master Abort—If the addressed target does not respond with an
HDEVSEL* assertion, then a master abort is flagged. In this case, the
RMA and MERROR bits in the PCI Configuration Register space will be
set and the PCI_BUS_STATUS[3] bit in the SYS_STAT Register will be
set.
3
Parity Error—If the data parity checked during read transfers is inconsis-
tent with the state of the HPAR signal, then a parity error is signaled. In
this case, the DPR and MERROR bits in the PCI Configuration Register
space will be set and the PCI_BUS_STATUS[2] bit in the SYS_STAT Reg-
ister will be set.
4
Interface Disabled—If the driver or application software on the PCI host
CPU has disabled, the RS8234 PCI bus master logic (using the M_EN bit
in the Command field of the PCI bus configuration registers), then any
attempt to perform a DMA transaction to the PCI bus will result in an
error. In this case, the MERROR and INTF_DIS bits in the PCI configura-