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11.0 PCI Bus Interface
11.6 PCI Configuration Space
RS8234
Datasheet for RS8234 xBR ServiceSAR
N8234DS1B
slave logic must arbitrate for access prior to performing any read or write transac-
tion. The slave logic also contains the PCI configuration registers. These registers
control the PCI slave and master interfaces, and may be read or written at any
time by the PCI host. The slave logic implements the synchronizers required for
rate-matching between the PCI bus clock and the internal RS8234 system clock.
Also, small FIFOs are used to speed up burst reads and writes performed by the
host processor to local resources, by buffering prefetched read data and absorbing
latency during consecutive writes.
In general, the PCI slave interface functions as a normal memory-mapped PCI
target, responding to Memory Read, Memory Write, Configuration Read, and
Configuration Write commands from any initiator on the PCI bus. Note that the
slave interface will only respond to Memory Read and Memory Write commands
if the MS_EN bit of the Command field in the PCI Configuration Register has
been set.
The PCI slave logic does not implement special cycle commands, or respond
to special cycles on the PCI bus. If a master performs a special cycle on the PCI
bus, the following occurs:
The slave logic never asserts HDEVSEL*.
Parity errors during the address phase of the special cycle command will
be reported to be asserting HSERR* in the normal fashion, if SE_EN and
PE_EN in the command register are both set.
Parity errors during the data phase are ignored.
11.6 PCI Configuration Space
In accordance with the PCI bus specification Revision 2.1, the RS8234 PCI bus
interface implements a 128-byte configuration register space. These configura-
tion registers can be used by the host processor to initialize, control, and monitor
the SAR bus interface logic. The complete definitions of these registers and the
relevant fields within them is given in the PCI bus specification, and will not be
repeated here. The descriptions and definitions of these register fields as imple-
mented in the RS8234 is shown in Chapter 13, RS8234 Registers.
11.7 Power Management
Power Management, as a defined class of functions, consists of mechanisms in
software and hardware to minimize system power consumption, manage system
thermal limits, and maximize system battery life. The RS8234 supports Power
Management on the PCI bus according to the PCI Bus Power Management Inter-
face Specification, Revision 1.0.
Power management states are defined as varying, distinct levels of power sav-
ings. The RS8234 device supports the two mandatory power states, D0 and D3, of
the PCI Bus Power Management Interface Specification. D0 is the maximum
powered state (on) and D3 is the minimum powered state (off). When in the D3
state, SYSCLK is turned off.