RS8234
ServiceSAR with xBR Traffic Management
ATM Service Segmentation and Reassembly Controller
The RS8234 Service Segmentation and Reassembly Controller
integrates ATM terminal functions, PCI Bus Master and Slave con-
trollers, and a UTOPIA interface with service specific functions in a
single package. The ServiceSAR Controller generates and terminates
ATM and automatically schedules cells for transmission. The RS8234
is targeted at 155 Mbit/s throughput systems where the number of
VCCs is relatively large, or the performance of the overall system is
critical. Examples of such networking equipment include Routers,
Ethernet switches, ATM Edge switches, or Frame Relay switches.
Service-Specific Performance Accelerators
The RS8234 incorporates numerous service-specific features
designed to accelerate and enhance system performance. As exam-
ples, the RS8234 implements Echo Suppression of LAN traffic via
LECID filtering, and supports Frame Relay DE to CLP interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the RS8234 supports multiple ATM
service categories. This includes CBR, VBR (both single and dual
leaky bucket), UBR, GFR (Guaranteed Frame Rate) and ABR. The
RS8234 manages each VCC independently. It dynamically schedules
segmentation traffic to comply with up to 8+CBR user-configured
scheduling priorities for the various traffic classes. Scheduling is
controlled by a Schedule Table configured by the user and based on a
user-specified time reference. ABR channels are managed in hard-
ware according to user programmable ABR templates. These tem-
plates tune the performance of the RS8234’s ABR algorithms to a
specific system’s or network’s requirements.
Multi-Queue Segmentation Processing
The RS8234’s Segmentation Coprocessor generates ATM cells
for up to 64 k VCCs at a line rate of up to 200 Mbit/sec for simplex
connections. The segmentation coprocessor formats cells on each
channel according to Segmentation VCC Tables, utilizing up to 32
independent Transmit Queues and reporting segmentation status on
a parallel set of up to 32 Segmentation Status Queues. The segmen-
tation coprocessor fetches client data from the host, formats ATM
cells while generating and appending protocol overhead, and for-
wards these to the UTOPIA port. The segmentation coprocessor
operates as a slave to the xBR Traffic Manager which schedules
VCCs for transmission.
Multi-Queue Reassembly Processing
The RS8234’s Reassembly Coprocessor stores the payload data
from the cell stream received by the UTOPIA port into host data buff-
ers. Using a dynamic lookup method which supports NNI or UNI
addressing, the reassembly coprocessor processes up to 64 k VCCs
simultaneously. The host supplies free buffers on up to 32 indepen-
dent Free Buffer Queues. The reassembly coprocessor performs all
CPCS protocol checks and reports the results of these checks + other
status data on one of 32 independent Reassembly Status Queues.
High Performance Host Architecture with Buffer Isolation
The RS8234 host interface architecture maximizes performance
and system flexibility. The device’s control and status queues enable
Host/SAR communication via write operations alone. This lowers
latency and PCI bus occupancy. Flexibility is achieved by supporting
a scalable peer-to-peer architecture. Multiple host clients may be
addressed by the SAR as separate physical or logical PCI peers. Seg-
mentation and reassembly data buffers on the host system are iden-
tified by buffer descriptors in SAR shared (or host) memory which
contain pointers to buffers. The use of buffer descriptors in this way
allows for isolation of data buffers from the mechanisms that handle
buffer allocation and linking. This provides a layer of indirection in
buffer assignment and management that maximizes system architec-
ture flexibility.
Designer Toolkit
Rockwell provides an evaluation environment for the RS8234
which provides a working reference design, an example software
driver, and facilities for generating and terminating all service catego-
ries of ATM traffic. This system accelerates ATM system develop-
ment by providing a rapid prototyping environment.
Functional Block Diagram
Multi-client
PCI Bus
UTOPIA Master/Slave
Local Bus
RS8234
PCI
DMA
Local Memory
Control/
Status
Cell
FIFO
Reassembly
Segmentation
CBR, VBR,
Timer
Counters
Traffic Manager
Patent Pending
Coprocessor
Interface
Master/
Slave
Co-
proc’r
ABR,UBR
Rx/Tx