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參數(shù)資料
| 型號(hào)： | (Z)PSD813F3 |
| 英文描述： | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位閃速存儲(chǔ)器，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 74/130頁(yè) |
| 文件大小： | 650K |
| 代理商： | (Z)PSD813F3 |
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PSD813F Famly
Prelimnary
70
9.5 Power Management
All three device families, the PSD813F, ZPSD813F, and ZPSD813FV offer configurable
power saving options. These options may be used individually or in combinations, as
follows:
J
All memory types in a PSD (Flash, EEPROM, and SRAM) are built with Zero-Power
technology. In addition to using special silicon design methodology, Zero-Power
technology puts the memories into standby mode when address/data inputs are not
changing (zero DC current). As soon as a transition occurs on an input, the affected
memory “wakes up”, changes and latches its outputs, then goes back to standby. The
designer does
not
have to do anything special to achieve memory standby mode when
no inputs are changing—it happens automatically.
When using ZPSD family devices, the PLD sections can also achieve standby mode
when its inputs are not changing.
J
Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals
from reaching the memories and PLDs. This feature is available on all three PSD813F
families. The APD unit is described in more detail in section 9.5.1.
Built in logic will monitor the address strobe of the MCU for activity. If there is no activity
for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode
(if enabled). Once in Power Down Mode, all address/data signals are blocked from
reaching PSD memories and PLDs, and the memories are deselected internally. This
allows the memories and PLDs to remain in standby mode even if the address/data
lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep
in mind that any unblocked PLD input signals that are changing states keeps the PLD
out of standby mode, but not the memories.
J
The PSD Chip Select Input (CSI) on all families can be used to disable the internal
memories, placing them in standby mode even if inputs are changing. This feature
does not block any internal signals or disable the PLDs. This is a good alternative to
using the APD logic, especially if your MCU has a chip select output. There is a slight
penalty in memory access time when the CSI signal makes its initial transition from
deselected to selected.
J
The PMMR registers can be written by the MCU at run-time to manage power. All three
families support “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related to
the composite frequency of the changes on their inputs (see Figures 34 and 34a).
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations.
Unique to the ZPSD813F and ZPSD813FV families is the Turbo Bit in the PMMR0
register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode
on). While Turbo Mode is disabled, the PLDs can achieve standby current when no
PLD inputs are changing (zero DC current). Even when inputs do change, significant
power can be saved at lower frequencies (AC current), compared to when Turbo Mode
is enabled. When the Turbo Mode is enabled, there is a significant DC current
component and the AC component is higher.
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode
The APD Unit, shown in Figure 31, puts the PSD into Power Down Mode by monitoring
the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity
on the address strobe stops, a four bit counter starts counting. If the address strobe
remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal
becomes active, and the PSD will enter into Power Down Mode, discussed next.
The
PSD813F
Functional
Blocks
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| (Z)PSD813F2(中文) | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM) |
| (Z)PSD813F3R(中文) | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無(wú)SRAM) |
| (Z)PSD813F2 | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲(chǔ)器，16K位SRAM) |
| (Z)PSD813F3R | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無(wú)SRAM) |
| 1.5KA24A | AUTOMOTIVE TRANSIENT VOLTAGE SUPPRESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F3-12JI | 制造商:WSI 功能描述: |
| ZPSD813F3-15J | 制造商:STMicroelectronics 功能描述:Flash in-system programmable microcontroller peripheral device |
| ZPSD813F3V-15J | 制造商:WSI 功能描述: |
| ZPSD813F3V-A-15J | 制造商:WSI 功能描述: |
| ZPSD813F4-12JI | 制造商:WSI 功能描述: |
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