參數(shù)資料
型號(hào): (Z)PSD813F3
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲(chǔ)器,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(shè)(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲(chǔ)器,16K的位的SRAM)
文件頁數(shù): 39/130頁
文件大?。?/td> 650K
代理商: (Z)PSD813F3
Prelimnary
PSD813F Famly
35
RESET
D0 - D7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
FLASH
DPLD
AND
FLASH
CPLD
INTERNAL
SELECTS
AND LOGIC
FLASH
PLD
PGR4
PGR5
PGR6
PGR7
Figure 11. Page Register
The
PSD813F
Functional
Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be
included in the Flash Memory, EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application
Note 57.
Figure 11 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
相關(guān)PDF資料
PDF描述
(Z)PSD813F2(中文) Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲(chǔ)器,16K位SRAM)
(Z)PSD813F3R(中文) Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲(chǔ)器,無SRAM)
(Z)PSD813F2 Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲(chǔ)器,16K位SRAM)
(Z)PSD813F3R Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲(chǔ)器,無SRAM)
1.5KA24A AUTOMOTIVE TRANSIENT VOLTAGE SUPPRESSOR
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