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CHAPTER 5 EXCEPTION PROCESSING
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5.4.10 Bus Error Exception
Cause
A Bus Error exception is raised by board-level circuitry for events such as bus time-out, local bus parity
errors, and invalid physical memory addresses or access types. This exception is not maskable.
A Bus Error exception occurs only when a cache miss refill, uncached reference, or unbuffered write
occurs synchronously.
Processing
The common interrupt vector is used for a Bus Error exception. The IBE or DBE code in the ExcCode
field of the Cause register is set, signifying whether the instruction caused the exception by an
instruction reference, load operation, or store operation.
The EPC register contains the address of the instruction that caused the exception, unless it is in a
branch delay slot, in which case the EPC register contains the address of the preceding branch
instruction and the BD bit of the Cause register is set to 1.
Servicing
The physical address at which the fault occurred can be computed from information available in the
System Control Coprocessor (CP0) registers.
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If the IBE code in the Cause register is set (indicating an instruction fetch), the virtual address is
contained in the EPC register (or 4 + the contents of the EPC register if the BD bit of the Cause
register is set to 1).
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If the DBE code is set (indicating a load or store), the virtual address of the instruction that caused
the exception (the address of the preceding branch instruction if the BD bit of the Cause register is
set to 1) is contained in the EPC register (or 4 + the contents of the EPC register if the BD bit of the
Cause register is set to 1).
The virtual address of the load and store instruction can then be obtained by interpreting the instruction.
The physical address can be obtained by using the TLBP instruction and reading the EntryLo register to
compute the physical page number.
At the time of this exception, the kernel reports the UNIX SIGBUS (bus error) signal to the current
process, but the exception is usually fatal.