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| 型號： | ZR36060PQC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG CODEC |
| 中文描述： | 綜合JPEG編解碼器 |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060PQC |
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6
Integrated JPEG CODEC
2.0 PIN DESCRIPTION
The ZR36060 is supplied in 100-pin PQFP package. The follow-
ing table lists the pins of the device and provides a concise
functional description of each.
Table 1: Pin Descriptions
Symbol
Type
Description
Code/Host Port (26 pins)
CODE[7:0
]
I/O
Code bus. In Code Master mode, this 8-bit bidirectional bus is used to read (write) the compressed data from (to) an external
code FIFO.
In 16-bit Code Slave mode, this is used as an extension (the MSB) of the DATA bus.
During and after RESET this bus is floating, with internal pull-ups.
CCS
O
Code Chip Select, used only in Code Master mode. This active-low output signal acts as a chip select signal from the ZR36060
to the external code FIFO. CCS
goes active at the start of a read or write cycle and remains active throughout the cycle. CCS
remains active continuously in back to back read or write cycles.
During and after RESET this pin is logic high.
COE
O
Code Read (output enable), used only in Code Master mode. This active-low output signal acts as a read strobe signal from
the ZR36060 to the external code FIFO. COE
goes active 0.5 VCLKx2 cycles after start of a read cycle. The CODE bus input
is latched on the rising edge of COE.
During and after RESET
this pin is logic high.
CWE
O
Code Write, used only in Code Master mode. This active-low output signal acts as a write strobe signal from the ZR36060 to
the external code FIFO. CWE
goes active 0.5 VCLKx2 cycles after start of a write cycle. CODE bus data is valid throughout
the strobe pulse and permits the external code FIFO to latch the data on the rising edge of CWE During and after RESET
pin is logic high.
this
CBUSY
I/O
Code FIFO Busy.
When the ZR36060 is the master of the code bus CBUSY
temporarily halt the transfer of compressed data.
When the ZR36060 is the slave of the code bus CBUSY
the internal code FIFO cannot be accessed, due to an empty/full condition (for compression/decompression modes respective-
ly). On deassertion, CBUSY
is driven high for one internal clock and then released to a floating condition (needs external pull-
up).
When the ZR36060 is connected to the ZR36057, CBUSY
is connected to the CBUSY input of the latter.
During and after RESET his pin is floating (input mode).
is an active-low input, used by the external code FIFO controller to
is an active-low output. It is asserted (low) by the ZR36060 to indicate
DATA[7:0]
I/O
Data bus. This 8-bit bidirectional bus is used to read/write to the internal memory of the ZR36060.
In Code Slave mode, it is also used to transfer the compressed data. In 16-bit Code Slave mode, the CODE bus is used as an
extension of the DATA bus.
During and after RESET this bus is floating with internal pullup.
ADDR[1:0
]
I
Address bus. This 2-bit bus is used by the host to access the code register (in Code Slave mode), or the indirect address/data
register which maps the 1Kbyte internal memory array of the ZR36060.
CS
I
Chip Select. This active-low input signal acts as a chip select signal from the host to the ZR36060.
WR
I
Write. This active-low input signal acts as a write pulse from the host to the ZR36060. The DATA (with CODE extension in 16-
bit Code Slave mode), is latched on the rising edge of WR.
RD
I
Read. This active-low input signal acts as a read pulse from the host to the ZR36060. The DATA (with CODE extension in 16-
bit Code Slave mode), is enabled as an output during the RD pulse so the host can latch the ZR36060 data on the rising edge
of RD.
ACK
O
Acknowledge. Used by the ZR36060 to notify the host that the current read or write strobe pulse can be completed.
During code access (Code Slave mode), the ZR36060 will not issue an ACK if the internal code FIFO is empty/full (in compres-
sion/decompression respectively).
On deassertion, ACK ist driven high for 1 VCLKx2 cycle and then released to a floating condition (needs external pull-up).
During and after RESET this pin is floating (logic high with pullup).
Video Port (25 pins)
Y7:Y0
I/O
In 16-bit video mode (Video8==0), these lines are the Luminance video lines. In 8-bit mode (Video8==1) these lines are lumi-
nance/chrominance lines, multiplexed in time according to the CCIR656 component order.
In compression these lines are inputs, while in decompression they are outputs.
During and after RESET this bus is floating with internal pullup.
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