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參數(shù)資料
| 型號： | ZR36060PQC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG CODEC |
| 中文描述： | 綜合JPEG編解碼器 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060PQC |
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11
Integrated JPEG CODEC
the ZR36060 counts Hstart pixels qualified by PVALID, and then
samples pixels qualified by PVALID until Hend.
The polarity of PVALID is programmable by means of the
PValPol parameter.
3.4 Video Scaling
The ZR36060 incorporates a scaler, that can scale the video in
the active area, horizontally and vertically, by simple ratios. It can
down-scale the video before it is compressed, and up-scale it
after it is decompressed. The result is to permit straightforward
implementation of “half screen area” and “quarter screen area”
compression.
The horizontal down- and up-scaling are accompanied by filter-
ing. Note that this filtering can not be disabled.
3.4.1 Horizontal down-scaling in compression
This is specified by the 2-bit HScale parameter. There are three
possible configurations:
HScale = 00b or 11b: No down-scaling
HScale = 01b: 2:1 decimation, with a 3-tap filter
HScale = 10b: 4:1 decimation, with a 5-tap filter
3.4.2 Vertical down-scaling in compression
This is specified by the 1-bit VScaleparameter:
VScale = 0b: No down-scaling
VScale = 1b:2:1 decimation, by line dropping
In the case of 2:1 vertical scaling, the second, fourth,...etc. lines
of the active area of the video field are dropped before the video
is compressed.
3.4.3 Horizontal up-scaling in decompression
As in compression, this is specified by HScale
HScale = 00b or 11b: No up-scaling
HScale = 01b: 2:1 interpolation
HScale = 10b: 4:1 interpolation
The interpolated samples are created by weighted-averaging of
two neighboring samples.
1. HPol = 0; VCLKPol = 0 (sample when VCLK = 0); PValPol = 1 (valid when PVALID = 1).
2. “Horizontal counter” represents an internal counter used to identify the active area.
3. PVALID granularity is one VCLK, in both 8- and 16-bit video interface modes.
4. PVALID may toggle only on a pixel boundary, in this figure when VCLK=0.
Figure 9. Video Data Formats, 8 and 16 bit
VCLKx2
VCLK
Y[7:0] Input
PVALID
8-Bit Video Interface
1
2
3
4
5
6
7
8
9
10
11
U0
Y0
V0
Min Width
Y1
U2
Y2
V2
Y3
12
13
HSYNC
Min Width
Y[7:0] Output
U0
Y0
Y1
Y2
V2
Y3
V0
U2
Horizontal Counter
1
0
2
3
16-Bit Video Interface
Y[7:0] Input
Y0
U0
UV[7:0] Input
Y1
V0
Y2
U1
V2
Y3
PVALID
Min Width
Min Width
Y[7:0] Output
Y1
Y0
Y2
Y3
UV[7:0] Output
V0
U0
U2
V2
Horizontal Counter
1
0
2
3
Notes:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC-LV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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