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參數(shù)資料
| 型號： | ZR36060PQC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG CODEC |
| 中文描述： | 綜合JPEG編解碼器 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 307K |
| 代理商： | ZR36060PQC |
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Integrated JPEG CODEC
6.11.1 Data Corruption during Decompression
If during the decompression of a field the ZR36060 senses a
data corruption event, it immediately asserts DATERR, then
continues the decompression process until it senses the EOI
(End Of Image) marker or the end of the active video area
(whichever occurs later). At this time it asserts END and enters
the IDLE state. The deassertion of END (upon START for the
next field) deasserts the DATERR signal.
1) If DATERR is not enabled as an interrupt requesting event
(i.e., it is cleared in the Interrupt Mask register), then the
ZR36060 samples START again, and if START is asserted a
new process begins.
2) If DATERR is enabled as an interrupt requesting event, JIRQ
is asserted together with the assertion of DATERR, and when
the ZR36060 completes the current process it enters the WAIT-
ISR state and remains “frozen” (without regard for START) until
the host reads the Interrupt Status register. At this time the
ZR36060 goes back to IDLE and is again ready to start a new
process, waiting for START.
In decompression the ZR36060 identifies a data corruption con-
dition if the strip buffer underflows, i.e.- insufficient blocks of
decompressed data to start outputting the first video line of a
strip when required.
3
Figure 38. Examples of ZR36060 Decompression (After Host Loaded Parameters & Load Command)
VSYNC
_active
_state
START
FRAME
RTBSY
DATERR
CSS
(code master)
CBUSY
(code slave)
DATA Bus
(CODE bus)
END
JIRQ
1
2
3
4
5
6
7
8
9
10
11
12
ODD
EVEN
ODD
EVEN
ODD
EVEN
ODD
EVEN
ODD
EVEN
ODD
EVEN
IDLE
WaitACT
EXP
i
i
IDLE
EXP
EXP
i
i
EXP
(w/error)
i
EXP
i
WaitISR
EXP
(w/error)
EXP
3
4
7
8
11
In field #1, START & FRAME asserted indicate to decompress on next ODD VSYNC (field #3). Code can be input immediately after START
assertion (filling CFIFO), to decode and fill with 8 lines of video the 1st. strip buffer before active video time arrive. After the 1st. strip is
completed, code is no longer fetched, and the ZR36060 waits for the active area of the next ODD field.
Field #3 decompression continues and complete, issue END and return to IDLE. RTBSY goes low after active area completes indicating
strip memory empty.
Field #4 is decompressed normally.
Begin field decompression, but system is too slow to feed new code data, so DATERR is asserted. Sampling of END and DATERR inform
the system of an illegal field. Since interrupt request on data error is enabled, ZR36060 assert JIRQ and wait until the host acknowledge the
JIRQ by reading the associated interrupt status register.
During this field, the host service the interrupt (ZR36060 de-assert JIRQ) and assert again START (w/o FRAME) for next field compression.
In this example, the host also disables interrupts after servicing this one.
Field #7 is decompressed. After END , system assert START for next field.
In Field #8 start to input code, but somewhere during the active area, the system is busy (without feeding new code) long enough that the
ZR36060 issue a DATERR (no JIRQ here since interrupts are disabled). Despite this situation the system continue to feed new code to the
ZR36060 until END which occurs only after next field #9 beginning (VSYNC assertion). Now START is sensed low meaning that next
decompression will happen on field #10 (skipping field #9).
Fields are decompressed normally. START is not asserted during field #11, therefore after END assertion the ZR36060 returns to IDLE and
wait for next operation.
1, 2.
3.
4.
5.
6.
7.
8, 9.
10, 11.
Notes:
i = go through IDLE & WAITACT)
5
8
10
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| ZR36067PQC-LV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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