參數(shù)資料
型號(hào)： ZR36060PQC
廠商： Electronic Theatre Controls, Inc.
元件分類(lèi)： Codec
英文描述： Integrated JPEG CODEC
中文描述： 綜合JPEG編解碼器
文件頁(yè)數(shù)： 12/46頁(yè)
文件大小： 307K
代理商： ZR36060PQC
10
Integrated JPEG CODEC
Note that in both 16-bit and 8-bit modes, the ZR36060 does not
output, nor expect to receive, control codes indicating timing
information, on its YUV video bus.
3.3 Video stream sampling and cropping
Only pixels within an active rectangle are sampled and com-
pressed (in compression) or output (in decompression), as
shown in Figure 6. The VSYNC signal indicates the beginning of
a new field (the VSYNC edge and polarity are configured by
FIVedge and VSPol). The Vstart and Vend parameters deter-
mine the first and last lines to be sampled in a field. The leading
edge of HSYNC indicates the beginning of a horizontal line (with
HSYNC polarity according to HSPol). The Hstart and Hend
parameters determine the first and last pixels to be sampled in
each line. Further processing such as formatting, scaling and
compression is done only to pixels within the active rectangle. In
decompression, outside the processed active area rectangle,
the video bus outputs a background color, specified by the
BackY, BackU, and BackV parameters.
Figure 7 and Figure 8 show the relationship of the active area to
VSYNC and HSYNC.
3.3.1 The PVALID control signal
The continuous video stream is usually used by encoders &
decoders for ‘real-time’ video capture and playback. However,
sometimes it may be desirable to ‘hold’ or not sample the video
pixels intermittently, especially when connected to a slow periph-
eral (such as a host interface compressing a still image, or a
memory controller) that cannot cope with the real-time pixel rate.
The PVALID signal can be used for this purpose.
PVALID acts as a pixel qualifier indicating the presence of ‘valid’
pixels on the bus (similar to the action of VCLK in 16-bit mode).
It can interrupt the video stream (in and out) for any period of
time with a resolution of VCLK, as shown in Figure 9. VCLK and
PVALID differ in that VCLK must always toggle at half the rate of
VCLKx2, while PVALID can maintain a continuous level. Only
pixels qualified by PVALID that are within the active rectangle
area are sampled. PVALID also acts as a ‘count enable’ to the
horizontal and vertical counters that implement Hstart, Hend,
Vstart, and Vend. For example, after the leading edge of HSYNC
Note: 16-bit video is shown with VCLKPol = 0, that is, sampling when VCLK = 0
Figure 5. Video Data Formats, 8 and 16 bit
VCLKx2
VCLK
Y[7:0]
Y[7:0]
UV[7:0]
8-Bit Video Interface
1
2
3
4
5
6
7
8
9
10
11
16-Bit Video Interface
U0
Y0
V0
Y1
U2
Y2
V2
Y3
U4
Y4
Y0
Y1
Y2
Y3
Y4
U0
V0
U2
V2
U4
BG Color
BG Color
BG Color
12
Figure 6. Video Pixel Stream
HSYNC
V
Active Area
(Rectangle)
Background Color
Hstart
Hend
V
V
Figure 7. Relationship of VSYNC and Active Video Area
VSYNC
Active Area
Vstart
a) VSPol = 0, FIVedge = 0
VSYNC
Active Area
Vstart
b) VSPol = 0, FIVedge = 1
VSYNC
Active Area
Vstart
c) VSPol = 1, FIVedge = 0
VSYNC
Active Area
Vstart
d) VSPol = 1, FIVedge = 1
The active video area must not overlap the VSYNC pulse. In other words, the
active area must always be contained between the trailing edge of VSYNC and
the next leading edge.
Note:
Figure 8. Relationship of HSYNC and active video area
HSYNC
Active Area
Hstart
a) HSPol = 0
HSYNC
Active Area
b) HSPol = 1
The line counting (for Vstart, Vend) always uses the leading edge of the HSYNC
pulse. Hstart is specified from the leading edge of HSYNC.
The active video area is allowed to partially overlap the HSYNC pulse. In other
words, Hstart could be before or after the trailing edge of HSYNC.
Note:
Hstart
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