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參數(shù)資料
| 型號： | ZR36060PQC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | Integrated JPEG CODEC |
| 中文描述： | 綜合JPEG編解碼器 |
| 文件頁數(shù)： | 18/46頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ZR36060PQC |
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Integrated JPEG CODEC
The EOI bit should only be used when decompressing in Code
Slave mode; in Code Master mode it is meaningless. It exactly
reflects the level of the EOI signal (with a positive logic).
The EOAV bit indicates that the last line of the active area (as
defined by the active area parameters), has been sampled (or
displayed) by the ZR36060. Note that in Auto Two-Pass Com-
pression mode, the EOAV bit is asserted only in the first pass.
The DATERR, END, EOI, and EOAV Interrupt Status bits are set
when the respective event occurs, and cleared together with
their respective pins (excepting EOAV) at the beginning of the
next process, i.e.- at the next START.
Note that Interrupt Status Register bits always reflect valid status
information regardless of their corresponding interrupts are
enabled in the Interrupt Mask Register.
When an interrupt-enabled event occurs, the JIRQ output is
asserted, and once the ZR36060 asserts END (completion of the
field process, i.e. compression or decompression of the current
field) it moves to the WAIT-ISR state (see the bubble diagram in
Figure 28). JIRQ remains asserted until the host reads the Inter-
rupt Status Register (see Figure 19). When this happens JIRQ is
deasserted and the ZR36060 returns to its IDLE state, where it
can sample START for the next field process.
The Interrupt Status Request register includes another pair of
bits, ProCount1:0, that are not related to interrupt requests, but
located in this register for convenience.
ProCount1:0 is the output of a modulo-4 cyclic counter that
advances with every start of a process (every rising edge of
END). It is never reset, except by RESET which initializes the
counter to 01b. It may be used by host controllers as an indica-
tion of a field dropped by the ZR36060 (e.g., when the ZR36060
outputs END of one field after the next one already started).
ProCount1:0 are read-only bits.
5.0 CODE INTERFACE
The code interface has two modes of operation:
Code Master mode
Code Slave mode
After RESET the ZR36060 defaults to Code Master mode. The
maximum throughput in Master mode is 30 MByte/sec; in 16-bit
Slave mode 16.7 MByte/sec; and in 8-bit Slave mode 8.3 MByte/
sec. The master mode is almost identical to the master mode of
the ZR36050. It is compatible with the ZR36057 PCI JPEG con-
troller and with the ZR36055 ISA JPEG controller. The slave
mode is compatible with common microprocessors or microcon-
trollers. The operating mode of the code port is selected through
the CodeMstr register bit (1b for Code Master mode, 0b for Code
Slave mode).
5.1 Master Mode
In this mode the compressed data is transferred on the 8-bit
CODE[7:0] bus, using the CCS, COE, and CWE outputs to
inform the system when a valid code transfer takes place, and
CBUSY input to stall further accesses until the system is avail-
able again. Master mode differs from the ZR36050’s master
mode in two minor ways:
The CFIS parameter, that determines the transfer cycle time
in this mode, is limited to the values 0b (one VCLKx2 per
transfer cycle) and 1b (2 VCLKx2 per transfer cycle)
The CAEN signal of the ZR36050 does not exist in the
ZR36060.
A Master Mode cycle starts with the activation of CCS, on the
rising edge of VCLKx2. CCS remains active throughout the bus
cycle and remains active continuously in back-to-back cycles. In
a read cycle, executed during decompression, COE goes active
0.5 VCLKx2 period after the beginning of the cycle and remains
active until the end of the cycle. Data is strobed in on the trailing
edge of COE. Similarly, in a write cycle, executed during com-
pression, CWE goes active 0.5 VCLKx2 period after the
beginning of the cycle and remains active until the end of the
cycle. Examples are shown in Figure 20 and Figure 21.
CBUSY is sampled one VCLKx2 before the beginning of each
bus cycle and if active, inhibits the bus cycle. If a bus cycle
started at the same time CBUSY was sampled active it com-
pletes normally.
Note: the CBUSY and EOI status bits are not valid in Code
Master mode.
Figure 19. Interrupt Acknowledgment by Reading
the Interrupt Status Register
CS
RD
WR
DATA[7:0]
ADDR[1:0]
ACK
STATUS Address
10
11
JIRQ
STATUS Data
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