參數(shù)資料
型號： ZL50022
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 4 K Digital Switch with Stratum 4E DPLL
中文描述： 增強為4 K數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 29/121頁
文件大小： 939K
代理商： ZL50022
ZL50022
Data Sheet
29
Zarlink Semiconductor Inc.
7.0 Data Input Delay and Data Output Advancement
Various registers are provided to adjust the input delay and output advancement for each input and output data
stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream.
If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The
sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating
at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set
to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate.
The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output
stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2
bit. By default, there is 0 output bit advancement.
Although input delay or output advancement features are available on streams which are operating in bi-directional
mode it is not recommended, as it can easily cause bus contention. If users require this function special, attention
must be given to the timing to ensure contention is minimized.
7.1 Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.
By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 31 (SICR0 - 31) as described in Table 45 on page 79. The input bit delay can range from
0 to 7 bits.
Figure 13 - Input Bit Delay Timing Diagram (ST-BUS)
FPi
STi[n]
Bit Delay = 0
(Default)
Channel 0
7
Channel 1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Channel 2
2 1 0
4 3
Last Channel
STi[n]
Bit Delay = 1
Channel 0
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
7
Channel 1
Channel 2
2 1 0
4 3
Last Channel
Bit Delay = 1
5
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
相關(guān)PDF資料
PDF描述
ZL50022GAC Enhanced 4 K Digital Switch with Stratum 4E DPLL
ZL50022QCC Enhanced 4 K Digital Switch with Stratum 4E DPLL
ZL50023 Enhanced 4 K Digital Switch
ZL50023GAC Enhanced 4 K Digital Switch
ZL50023QCC Enhanced 4 K Digital Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50022_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 4 K Digital Switch with Stratum 4E DPLL
ZL50022GAC 制造商:Microsemi Corporation 功能描述:4K WITH RATE CONVERSION AND S4 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 4K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 4K-CH ENH 256PBGA
ZL50022GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 4K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 4K-CH ENH 256PBGA
ZL50022QCC 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:4K WITH RATE CONVERSION AND S4E DPLL - Trays
ZL50022QCG1 制造商:Microsemi Corporation 功能描述:PB FREE 4K +RATE CONVERSION & 256L LQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 4K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 4K-CH ENH 256LQFP
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*