參數資料
型號: ZL30121GGG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數字傳輸電路
英文描述: SONET/SDH Low Jitter System Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝: 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁數: 16/30頁
文件大?。?/td> 326K
代理商: ZL30121GGG
ZL30121
Data Sheet
16
Zarlink Semiconductor Inc.
All sync inputs (
sync0 to sync2
) are continuously monitored to ensure that there is a correct number of reference
clock cycles within the frame pulse period.
1.5 Output Clocks and Frame Pulses
The ZL30121 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (
diff0_p/n,
diff1_p/n
), two SONET/SDH LVCMOS (
sdh_clk0, sdh_clk1
) output clocks, and four programmable LVCMOS
(
p0_clk0, p0_clk1, p1_clk0, p1_clk1
) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH
frame pulse outputs (
sdh_fp0, sdh_fp1
) and two LVCMOS programmable frame pulses (
p0_fp0, p0_fp1
) are also
available.
The feedback clock (
fb_clk
) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30121 to have two independent timing paths.
Figure 6 - Output Clock Configuration
DPLL2
p0_clk0
p0_fp0
p0_clk1
p0_fp1
P0
Synthesizer
DPLL1
p1_clk0
p1_clk1
P1
Synthesizer
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
SONET/SDH
APLL
diff0
diff1
Feedback
Synthesizer
fb_clk
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相關代理商/技術參數
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