參數(shù)資料
型號(hào): ZL30406QGC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Digital Multimeter Clamp Battery Size Code:9V; Current Measuring Range:40.00/400.0A; Current Setting AC:400A; Current Setting DC:400A; Resistance Measuring Range:400 Ohm, 4000 - 40 - 400 kOhm; Voltage Measuring Range AC:600 V RoHS Compliant: NA
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64
文件頁(yè)數(shù): 1/21頁(yè)
文件大?。?/td> 307K
代理商: ZL30406QGC
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Meets jitter requirements of Telcordia GR-253-
CORE for OC-48, OC-12, and OC-3 rates
Meets jitter requirements of ITU-T G.813 for STM-
16, STM-4 and STM-1 rates
Provides four LVPECL differential output clocks at
77.76 MHz
Provides a CML differential clock programmable
to 19.44 MHz, 38.88 MHz, 77.76 MHz and
155.52 MHz
Provides a single-ended CMOS clock at
19.44 MHz
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
Applications
SONET/SDH line cards
Network Element timing cards
Description
The ZL30406 is an analog phase-locked loop (APLL)
designed to provide rate conversion and jitter
attenuation for SDH (Synchronous Digital Hierarchy)
and
SONET
(Synchronous
networking equipment. The ZL30406 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1
rates and ITU-T G.813 STM-16, STM-4 and STM-1
rates.
Optical
Network)
The ZL30406 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 77.76 MHz, a CML differential
clock programmable to 19.44 MHz, 38.88 MHz,
77.76 MHz and 155.52 MHz and a single-ended
CMOS clock at 19.44 MHz. The output clocks can
be individually enabled or disabled.
February 2005
Ordering Information
ZL30406QGC
ZL30406QGC1
64 Pin TQFP
64 Pin TQFP*
Trays
Trays
*Pb Free Matte Tin
-40
°
C to +85
°
C
Figure 1 - Functional Block Diagram
Frequency
& Phase
Detector
VCO
C77oP/N-A
Interface
Circuit
LPF
FS1-2
C77oP/N-B
C77oP/N-C
VDD
GND
VCC
C77oP/N-D
C19o
C19oEN
OC-CLKoP/N
OC-CLKoEN
C155o
CML-P/N outputs
Loop
Filter
C77oEN-C
C19i
C77o
,
C19o, C38o,
C77oEN-B
BIAS
C77oEN-A
C77oEN-D
Output
19.44MHz
15
Reference &
Bias circuit
ZL30406
SONET/SDH Clock Multiplier PLL
Data Sheet
相關(guān)PDF資料
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參數(shù)描述
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