參數(shù)資料
型號(hào)： ZL30121GGG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： SONET/SDH Low Jitter System Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝： 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁(yè)數(shù)： 12/30頁(yè)
文件大?。?/td> 326K
代理商： ZL30121GGG
ZL30121
Data Sheet
12
Zarlink Semiconductor Inc.
1.2 DPLL Mode Control
Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal, and holdover. The
mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30121 will enter in the Normal (locked) mode.
Supported Output
Frame Pulse
Frequencies
As listed in Table 4
As listed in Table 4 for p0_fp0, p0_fp not
synchronized to sync reference.
External Status Pin
Indicators
Lock, Holdover
None
1. Limited to 14 Hz for 2 kHz references)
2. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies greater than
8 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to 8 kHz, the loop bandwidth = 56 Hz. The loop bandwidth is
equal to 14 Hz for reference frequencies of 2 kHz.
Feature
DPLL1
DPLL2
Table 1 - DPLL1 and DPLL2 Features
Reset
Another reference is
qualified and available
for selection
Phase lock on
the selected
reference is
achieved
Lock
Acquisition
No references are
qualified and available
for selection
Free-Run
Holdover
Selected reference
fails
All references are monitored for
frequency accuracy and phase
regularity, and at least one
reference is qualified.
Normal
(Locked)
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參數(shù)描述
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ZL30122GGG 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 64CABGA - Trays 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 64CABGA
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