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參數(shù)資料
| 型號： | ZL30101QDC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 3 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 28/34頁 |
| 文件大?。?/td> | 534K |
| 代理商： | ZL30101QDC |
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ZL30101
Data Sheet
28
Zarlink Semiconductor Inc.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within
Out-of-Range limits.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Figure 16 - Input to Output Timing
AC Electrical Characteristics* - Input Timing for REF0 and REF1 References (see Figure 16)
Characteristics
Symbol
Min.
Typ.
Max.
Units
1
8 kHz reference period
t
REF8KP
t
REF1.5P
t
REF2P
t
REF8P
t
REF16P
t
REFW
121
125
128
μ
s
2
1.544 MHz reference period
338
648
950
ns
3
2.048 MHz reference period
263
488
712
ns
4
8.192 MHz reference period
63
122
175
ns
5
16.384 MHz reference period
38
61
75
ns
6
reference pulse width high or low
15
ns
AC Electrical Characteristics* - Input to Output Timing for REF0 and REF1 References (see Figure 16)
Characteristics
Symbol
Min.
Max.
Units
1
8 kHz reference input to F8/F32o delay
t
REF8KD
t
REF1.5D
t
REF1.5_F8D
t
REF2D
t
REF2_F8D
t
REF8D
t
REF8_F8D
t
REF16D
t
REF16_F8D
0.7
2.0
ns
2
1.544 MHz reference input to C1.5o delay
2.4
3.0
ns
3
1.544 MHz reference input to F8/F32o delay
2.5
3.3
ns
4
2.048 MHz reference input to C2o delay
2.0
3.0
ns
5
2.048 MHz reference input to F8/F32o delay
2.2
3.3
ns
6
8.192 MHz reference input to C8o delay
5.2
6.2
ns
7
8.192 MHz reference input to F8/F32o delay
5.5
6.3
ns
8
16.384 MHz reference input to C16o delay
2.6
3.3
ns
9
16.384 MHz reference input to F8/F32o delay
-28.0
-27.2
ns
REF0/1
t
REF<xx>P
t
REF8kD
, t
REF<xx>_F8D
t
REFW
t
REF<xx>D
t
REFW
F8_32o
output clock with
the same
frequency as REF
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