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參數(shù)資料
| 型號： | ZL30101QDC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 3 System Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 534K |
| 代理商： | ZL30101QDC |
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ZL30101
Data Sheet
12
Zarlink Semiconductor Inc.
Figure 5 - Out-of-Range Thresholds
The precise frequency monitor’s failure thresholds are compatible with Telcordia GR-1244-CORE Stratum 3 as
shown in Figure 5. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit eliminates phase transients on the output clock that may occur during reference switching
or the recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover
mode.
The delay value can be reset by applying a logic low pulse to the TIE corrector circuit clear pin (TIE_CLR). A
minimum reset pulse width is 20 ns. This results in a phase alignment between the input reference signal and the
output clocks and frame pulses as shown in Figure 16 on page 28 and Figure 17 on page 30. The speed of the
phase alignment correction is limited to 61
μ
s/s when BW_SEL=0. Convergence is always in the direction of least
phase travel. In general the TIE correction should not be exercised when Holdover mode is entered for short time
periods. TIE_CLR can be kept low continuously. In that case the output clocks will always be aligned with the
selected input reference. This is illustrated in Figure 6.
0 ppm
+4.6 ppm
-4.6 ppm
0
7.4
12
9.2
4.6
4.6
-4.6
-13.8
-15
-10
0
-5
5
15
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
10
-9.2
-12
16.6
13.8
-4.6
-7.4
-16.6
C20: 20 MHz master clock on OSCi
C20
C20
C20 Clock Accuracy
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30101QDG1 | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 64TQFP - Trays |
| ZL30102 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK SYNTHESIZER SGL 64TQFP - Trays |
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
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