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ZL20250
Data Sheet
41
Zarlink Semiconductor Inc.
2.13.1 Fractional N Compensation
Bits 23:16 set the value for fractional N compensation in the UHF PLL with bit 23 as MSB. The value for the
compensation is dependent on a number of parameters which are described in the synthesizer section.
2.13.2 PLL Lock detect counters
These 4 bit counters count the consecutive comparison cycles where the lock detect circuit gives an in-lock result.
When the counter reaches its programmed count then that PLL is deemed to have achieved full lock. This prevents
spurious false in-lock signals while the PLL is achieving lock up. There are separate counters for the UHF, Rx VHF
and Tx VHF PLLs which are programmed as shown above. Bits 15,11,7 are the MSB's for the UHF, Rx VHF and Tx
VHF PLL lock detector counters respectively. A non zero value must be programmed for the lock detect to operate
correctly.
3.0 Absolute Maximum Ratings
This device is sensitive to ESD. Most pins have an ESD rating greater than 2000V (Human Body Model HBM),
however some pins have limited protection (800 to 2000V )in order to meet the RF performance. Anti-static
precautions should be used when handling this device.
4.0 Operating Conditions
Device operation is guaranteed under the following coonditions:
Supply Voltage
-0.3 to 3.6V
Voltage applied to any pin
-0.3 to Vcc + 0.3 V
Operating Temperature
-40°C to 85°C
Storage Temperature
-55°C to 125°C
Max Junction Temperature
125°C
Condition
Min
Value
Typ
Max
Units
Comments
General
Supply Voltage
2.7
3.3
V
Operating Temperature
-40
+85
°C
Logic Input Voltage High – VIH
0.8Vcc
Volts
Logic Input Voltage Low – VIL
0.2Vcc
Volts
TCXO Reference Frequency
Frequency
13.0
MHz
GSM
Frequency
14.4
MHz
IS136
Frequency
19.44
MHz
IS136