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ZL20250
Data Sheet
29
Zarlink Semiconductor Inc.
Note 1:
Not required if driving external receive mixer direct from UHF VCO.
The receive register contains all bits required when in receive mode: the transmit register contains all bits required
in duplex mode. The Enable1 configuration register contains all bits required to power up oscillators and synthesizers
in both receive and duplex mode. The Enable2 configuration register contains all bits required to power up the
complete receive and duplex modes (this register can be set to all '1's if preferred).
The following words should therefore be programmed on the serial bus (Hex format):
Receive register (0)
Transmit register (1)
Enable1 Config. register (2)
Enable2 Config. register (3)
5DE200
5DFFF1
188262
5DFFF3
2.2 Operating Register Address 4
This registers selects internal setups for example IS136 or GSM. The bits are assigned for control of receive and
transmit bits as shown below:
The function of the receive bits is shown below:
Bit 23 RX<7> is only applicable when VCO divide by 2 mode is selected in register 5.
7
Transmit quadrature modulator
0
1
0
1
6
Transmit VHF PLL
0
1
1
1
5
Transmit VHF VCO
0
1
1
1
4
Transmit up-converter IF input
0
1
0
1
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RX<7:0>
TX <11:0>
0
1
0
0
Receive Set Up
Transmit Set Up
Address
Register
Bit No.
Control
Bit
Action if '0'
Action if '1'
23
RX<7>
Receive DLL disabled
Receive DLL enabled
22
RX<6>
Bandpass Filter BW = +/- 20 kHz
Bandpass Filter BW = +/- 16 kHz
21
RX<5>
GSM Filters active
Receive GSM filters bypassed
20
RX<4>
LO output = 900 MHz
LO Output = 1900 MHz
19
RX<3>
Receive output dc bias (I/Q) = 1.25 V
Receive output dc bias (I/Q) = Vcc/2
18
RX<2>
IS136 Mode IF1 Input enabled
GSM Mode IF0 Input enabled
17
RX<1>
AMPS
IS136
16
RX<0>
Not used
Not used
Bit
Circuit Section
Receive
Addr 0
Transmit
Addr 1
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
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