參數(shù)資料
型號(hào): ZL20250
廠商: Zarlink Semiconductor Inc.
英文描述: 2.5G Multimode Transceiver
中文描述: 2.5G的多模收發(fā)器
文件頁數(shù): 40/56頁
文件大?。?/td> 392K
代理商: ZL20250
ZL20250
Data Sheet
40
Zarlink Semiconductor Inc.
For example for a divide ratio of 13235, the binary equivalent is: 11001110110011. The programming values can be
selected as shown below:
2.10 Receive VHF PLL Reference Divider Programming Register - Address 12
Bits 23:19 are unused and should be set to '0'
Bit 18 selects common reference divider for VHF receive and transmit PLLs ('0' to select). If a common reference
divider is selected then the transmit VHF reference divider is used which must be programmed in register 13.
Bits 17:4 set the Reference divider value (Bit 17 = MSB)
2.11 Transmit VHF PLL Divider Programming Register - Address 13
Bits 23:21 are unused and should be set to '0'
Bits 20:8 set M counter value (Bit 20 = MSB)
Bits 7:4 set A counter value - max value = 15 (Bit 7 = MSB)
Programming is identical to that for the receive VHF PLL register 11.
2.12 Transmit VHF PLL Reference Divider Programming Register Address 14
Bits 23:18 are unused and should be set to '0'
Bits 17:4 set the Reference counter value (Bit 17 = MSB)
2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15
Bit No.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
Count Value
0
0
0
1
1
0
0
1
1
1
0
1
1
0
0
1
1
M
A
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
0
0
X
X
X
X
X
RS
Receive VHF PLL Reference Counter Value
Address
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0
1
X
X
X
M Counter Value
A Counter Value
Address
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
1
0
X
X
X
X
X
X
Transmit VHF PLL Reference Counter Value
Address
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
Fractional N Compensation
UHF PLL
Lock Count
Transmit VHF PLL
Lock Count
Receive VHF PLL
Lock Count
Address
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