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參數資料
| 型號： | ZL20250 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 2.5G Multimode Transceiver |
| 中文描述： | 2.5G的多模收發(fā)器 |
| 文件頁數： | 27/56頁 |
| 文件大小： | 392K |
| 代理商： | ZL20250 |
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ZL20250
Data Sheet
27
Zarlink Semiconductor Inc.
A feature of this programming approach is that once a phone operating mode has been selected and set up via the
serial bus, all power control can then be via the TX RXB, ENABLE1 and ENABLE2 control pins. Alternatively full
power control is possible via the 3 wire serial bus without the use of any external control pins.
If ENABLE1 and ENABLE2 are both low then the device is in Sleep mode. No circuits will be enabled unless either
ENABLE1 or ENABLE2 are high regardless of the contents of the receive and transmit registers.
An example of how these control bits can be used, is that the oscillators and PLL circuits can be powered up and
allowed to settle prior to powering up the complete transmit or receive path. In the case of the receive path the UHF
synthesizer, UHF LO input buffer, UHF LO Buffer and Receive VHF VCO, Receive VHF PLL bits would be set in the
ENABLE1 Configuration register. The ENABLE2 Configuration register would contain these bits plus the remainder
of the receive path bits, Receive IF input, Receive AGC amplifier, Receive quadrature down-converter and receive
baseband section.
This is demonstrated in the following examples.
2.1.1 Power Control Modes - TDMA (GSM and IS136)
In a TDMA system the transceiver will either operate in receive only, or transmit only mode. It is assumed that an
interim power on state will be used during which the oscillators and PLLs will be set up, and allowed to settle prior
to activating the full signal path. The suggested programming for the power control registers (0 - 3) is shown in the
table below.
Bit
Circuit
Section
Receive
Addr 0
Transmit
Addr 1
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Comments
23
Not used
0
0
0
0
22
Receive Baseband section
1
0
0
1
21
UHF LO Buffer
0
0
0
0
Note 1
20
Receive VHF VCO
1
0
1
1
19
UHF synthesizer
1
1
1
1
18
Receive RSSI circuit
0
0
0
0
Note 2
17
Not used
0
0
0
0
16
Receive Quadrature down-converter
1
0
0
1
15
Receive VHF PLL
1
0
1
1
14
Receive IF input
1
0
0
1
13
Receive AGC amplifier
1
0
0
1
12
Transmit reconstruction filters
0
1
0
1
11
Transmit RF
0
1
0
1
10
Transmit UHF LO
0
1
0
1
9
UHF LO input buffer
1
1
1
1
8
Transmit IF
0
1
0
1
7
Transmit quadrature modulator
0
1
0
1
6
Transmit VHF PLL
0
1
1
1
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