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ZL20250
Data Sheet
23
Zarlink Semiconductor Inc.
prescaler ratio is 17 assuming A > 0; when the A counter reaches zero the prescaler ratio is 16 until the M counter
reaches zero. The complete process is then repeated.
The total divide ratio (N) for this type of counter is given by
N = 16*M + A
M is always greater then A
The values of M and A can be easily calculated from the total divide ratio N.
M = INT (N/16)
A = N - 16*M
The maximum value for A is 15 and M must always be greater than A.
The VHF PLLs do not have fractional N capability however it is recommended that thay are operated at as high a
comparison frequency as allowed by the chosen frequency plan to minimise spurs levels.
Both VHF synthesizers have lock detection circuits. These operate in the same way as described for the UHF
synthesizer.
1.6 Internal Clock Generation
ZL20250 can use 14.4 MHz or 19.44MHz reference frequency (standard for IS136), or 13 MHz or 26 MHz (standard
for GSM). The appropriate reference must be programmed via the serial bus. The clock signals for the switched
capacitor filters and FM demodulator are generated from the reference TCXO signal. The internal divide ratios are
switched to give the optimum ratio. For dual mode applications (GSM/IS136) a 13 MHz or 26 MHz reference should
be used. This will give a small error in the switched capactor clock frequency used for IS136 but has negligible effect
on performance.
1.7 VHF VCO
ZL20200 has two VHF VCOs which operate with the VHF PLLs to provide the IF LO signals for both receive and
transmit IF signals. The oscillators are a differential design and require an external tank circuit. A basic circuit with
varactor is shown in Figure 13. It is recommended to include series resistors (eg 43 ohms) in each arm of the tank
circuit to prevent any spurious high frequency oscillation due to parasitic capacitances.
Figure 13 - Typical VCO Tank Circuit
nm
33n
18p
18p
43R
43R
10k
10k
From PLL
Loop
Filter
VCO+
VCO-