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參數(shù)資料
| 型號： | ZL10311DTV-SOC |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Digital Television DVB-T-On-a-Chip Processor |
| 中文描述： | 數(shù)字電視的DVB - T -上一芯片處理器 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | ZL10311DTV-SOC |
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ZL10310/ZL10311
Data Sheet
34
Zarlink Semiconductor Inc.
6.15 Power Supply Pins
The ZL10310 and ZL10311 devices operate from 3 voltages; 3.3V for the Input/Outputs, 2.5V for the Video DACs
and 1.8V for the SoC Core. The table below shows the pins to which each of the supply voltages should be
connected.
Pin Name
Pin No.s
Description
Nominal Voltage
Supply
GND
A1, A2, A8, A14, A19, A26,
B2, B25, B26, C3, C24, D4,
D9, D13, D18, D23, H1,
H26, J4, J23, N1, N23, P4,
P26, V4, V23, W1, W26,
AC4, AC9, AC14, AC18,
AC23, AD3, AD24, AE1,
AE2, AE25, AF1, AF8,
AF13, AF19, AF25, AF26
Digital Ground
(used in parallel with Thermal_GND pins)
0V
VDD_Core
D10, D12, D15, D17, K4,
K23, M4, M23, R4, R23, U4,
U23, AC10, AC12, AC15,
AC17
VDD Supplies to ZL10310/ZL10311 Core
+1.8V
wrt GND
VDD_IO
AC5, AC7, AC8, AC19,
AC20, AC22, E23, G23,
H23, W23, Y23, AB23, D5,
D7, D8, D19, D20, D22, E4,
G4, H4, W4, Y4, AB4
VDD Supplies to ZL10310/ZL10311 I/O
pins
+3.3V
wrt GND
AUD_GNDA0
B14
Analog GND for Audio PLL 1
0V
AUD_GNDA1
C15
Analog GND for Audio PLL 2
0V
AUD_VDDA0
B15
Analog VDD for Audio PLL 1
+1.8V
wrt
AUD_GND
AUD_VDDA1
A16
Analog VDD for Audio PLL 2
+1.8V
wrt
AUD_GND
CLK_GNDA
A22
Analog GND for System Clock PLL
(27MHz)
0V
CLK_VDDA
B20
Analog VDD for System Clock PLL
(27MHz)
+3.3V
wrt
CLK_GND
COFDM_GNDA
A10
Analog GND for COFDM PLL
(20.48MHz)
0V
COFDM_VDDA
D11
Analog VDD for COFDM PLL
(20.48MHz)
+1.8V
wrt
COFDM_GND
DAC1_AGND
AE12, AD14, AE16
Analog GND for Video Triple-DAC 1
0V
DAC1_AVDD
AC13, AF14, AF15, AE17
Analog VDD for Video Triple-DAC 1
+2.5V
wrt
DAC1_AGND
DAC2_AGND
AF09, AE08, AE07
Analog GND for Video Triple-DAC 2
0V
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相關(guān)代理商/技術(shù)參數(shù) |
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| ZL10311GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
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