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參數(shù)資料
| 型號： | ZL10312UBH |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, UUC20 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 340K |
| 代理商： | ZL10312UBH |
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
On-chip digital filtering supports 1 - 45 MSps
symbol rates
On-chip 60 or 90 MHz dual-ADC
High speed scanning mode for blind symbol
rate/code rate acquisition
Automatic spectral inversion resolution
High level software interface for minimum
development time
Up to ±22 MHz LNB frequency tracking
DiSEqC v2.2: receive/transmit for full control of
LNB, dish and other components
Compact 64 pin LQFP package (7 x 7 mm)
Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR
requirements
Applications
DVB 1 - 45 MSps compliant satellite receiver
DSS 20 MSps compliant satellite receivers
SMATV trans-modulators. (Single Master
Antenna TV)
Satellite PC applications
Description
The
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
ZL10312
is
a
QPSK/BPSK
1 - 45 MSps
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
November 2004
Ordering Information
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
64 Pin LQFP
64 Pin LQFP
64 Pin LQFP*
Die supplied in wafer form**
Trays, Bake & Drypack
Tape & Reel
Trays, Bake & Drypack
*Pb Free Matte Tin
**
Please contact Sales for further details
0
°
C to +70
°
C
ZL10312
Satellite Demodulator
Data Sheet
Figure 1 - Functional Block Diagram
I I/P
Q I/P
Dual ADC
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
MPEG/
DSS
Packets
Bus I/O
2-Wire Bus
Interface
Acquisition
Control
Clock Generation
Analog
AGC
Control
DVB
DSS
FEC
相關PDF資料 |
PDF描述 |
|---|---|
| ZL10312 | Satellite Demodulator |
| ZL10313QCG | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:24; Mounting Type:1U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
| ZL10313QCG1 | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:48; Mounting Type:2U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
| ZL10313UBH | WIRE, PTFE, A, WHITE, 7/.012MM, 100M; Area, conductor CSA:0.079mm2; Conductor make-up:7/0.12mm; Voltage rating, AC:300V; Current rating:3A; Colour, primary insulation:White; Material, primary insulation:PTFE; Diameter, RoHS Compliant: Yes |
| ZL10313 | Satellite Demodulator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10313 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313UBH | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10320 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television PVR-on-a-Chip Processor |
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