參數(shù)資料
型號(hào)： ZL10311DTV-SOC
廠商： Zarlink Semiconductor Inc.
英文描述： Digital Television DVB-T-On-a-Chip Processor
中文描述： 數(shù)字電視的DVB - T -上一芯片處理器
文件頁(yè)數(shù)： 14/40頁(yè)
文件大?。?/td> 670K
代理商： ZL10311DTV-SOC
ZL10310/ZL10311
Data Sheet
14
Zarlink Semiconductor Inc.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
5V tolerant connection to allow use of 5V Tuner devices
Multiplex setup with COFDM Register Bit 0 = '1'
Multiplex setup with CICSEL3 Register Bits 9:11 = '111'
Multiplex setup with CICSEL3 Register Bit 6 = '1', and GPIS2 Register Bits 24:25 = '01'
Multiplex setup with COFDM Register Bit 0 = '0'
External pull-up to Tuner Vdd PSU required on GPPx lines.
The ADC_IN [0:9] and EXT_IN [0:9] inputs on the Front End interface are configured as “Big Endian”. This means that bit [0]
is the Most Significant Bit (MSB) for the multiplexed functions mapped to that pin.
When the ADC_IN [0:9] and EXT_IN [0:9] pins are used to provide various alternative inputs within one application, then each
set of inputs must have a tri-state buffer. The enables for these buffers should then be controlled by general purpose I/O pins.
Note 8:
6.3 Video DAC Outputs
Note 1:
Video outputs capable of driving between 37.5ohm and 75ohm loads.
ADC_IN[8]
AA03
COFDM_ADCIN[0]
(LSB)
I
COFDM Digital Input from Ext. ADC -
Data Bit 0 (LSB)
2, 5, 7
DV2_IN_DATA[0]
(LSB)
I
Reserved
7
ED2_MOVAL
I
External Demodulator 1 Digital Input -
Data Valid Input
ADC_IN[9]
AC02
DV2_IN_Pixel_Clk
I
Reserved
ED2_MOCLK
I
External Demodulator 1 Digital Input - Clock Input
Pin Name
Pin No.
Pin
Type
Description
Notes
DAC_OP0
AE15
O
Video Triple-DAC 1 output 1.
1, 2
DAC_OP1
AD15
O
Video Triple-DAC 1 output 2.
1, 2
DAC_OP2
AD13
O
Video Triple-DAC 1 output 3.
1, 2
DAC_OP3
AD10
O
Video Triple-DAC 2 output 1.
1, 2
DAC_OP4
AF06
O
Video Triple-DAC 2 output 2.
1, 2
DAC_OP5
AF10
O
Video Triple-DAC 2 output 3.
1, 2
DAC1_CREF_OUT
AF11
O
De-coupling for triple DAC 1 - to GND
DAC1_GREF_OUT
AF17
O
De-coupling for triple DAC 1 - to AVDD
DAC1_RREF_OUT
AE13
O
Gain control for triple DAC 1.
3
DAC1_VREF_IN
AE14
I
Voltage reference input (1.2V) for Video Triple-DAC 1.
4
DAC2_CREF_OUT
AE11
O
De-coupling for triple DAC 2 - to GND
DAC2_GREF_OUT
AF05
O
De-coupling for triple DAC 2 - to AVDD
DAC2_RREF_OUT
AE09
O
Gain control for triple DAC 2.
3
DAC2_VREF_IN
AF07
I
Voltage reference input (1.2V) for Video Triple-DAC 2
4
Pin Name
Pin
No.
Function
Pin
Type
Description
Notes
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